From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1Nocof-0006Lg-QQ for qemu-devel@nongnu.org; Mon, 08 Mar 2010 08:16:14 -0500 Received: from [199.232.76.173] (port=55937 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1Nocod-0006Ky-RA for qemu-devel@nongnu.org; Mon, 08 Mar 2010 08:16:11 -0500 Received: from Debian-exim by monty-python.gnu.org with spam-scanned (Exim 4.60) (envelope-from ) id 1Nocob-0001ka-G7 for qemu-devel@nongnu.org; Mon, 08 Mar 2010 08:16:11 -0500 Received: from mx20.gnu.org ([199.232.41.8]:52281) by monty-python.gnu.org with esmtps (TLS-1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1Nocoa-0001d4-SK for qemu-devel@nongnu.org; Mon, 08 Mar 2010 08:16:09 -0500 Received: from mail.codesourcery.com ([38.113.113.100]) by mx20.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1NoclI-0001c4-QF for qemu-devel@nongnu.org; Mon, 08 Mar 2010 08:12:45 -0500 From: Paul Brook Subject: Re: [Qemu-devel] [PATCH] Inter-VM shared memory PCI device Date: Mon, 8 Mar 2010 13:04:45 +0000 References: <1267833161-25267-1-git-send-email-cam@cs.ualberta.ca> <201003072254.00040.paul@codesourcery.com> <20100308014537.GA24024@shareable.org> In-Reply-To: <20100308014537.GA24024@shareable.org> MIME-Version: 1.0 Content-Type: Text/Plain; charset="iso-8859-1" Content-Transfer-Encoding: 7bit Message-Id: <201003081304.45862.paul@codesourcery.com> List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Cam Macdonell , kvm@vger.kernel.org > However, coherence could be made host-type-independent by the host > mapping and unampping pages, so that each page is only mapped into one > guest (or guest CPU) at a time. Just like some clustering filesystems > do to maintain coherence. You're assuming that a TLB flush implies a write barrier, and a TLB miss implies a read barrier. I'd be surprised if this were true in general. Paul