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From: Paul Brook <paul@codesourcery.com>
Subject: Re: [Qemu-devel] [PATCH] Inter-VM shared memory PCI device
Date: Wed, 10 Mar 2010 00:03:38 +0000
References: <1267833161-25267-1-git-send-email-cam@cs.ualberta.ca>
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To: Jamie Lokier <jamie@shareable.org>
Cc: Cam Macdonell <cam@cs.ualberta.ca>, qemu-devel@nongnu.org, kvm@vger.kernel.org, Avi Kivity <avi@redhat.com>

> > In a cross environment that becomes extremely hairy.  For example the x86
> > architecture effectively has an implicit write barrier before every
> > store, and an implicit read barrier before every load.
> 
> Btw, x86 doesn't have any implicit barriers due to ordinary loads.
> Only stores and atomics have implicit barriers, afaik.

As of March 2009[1] Intel guarantees that memory reads occur in order (they 
may only be reordered relative to writes). It appears AMD do not provide this 
guarantee, which could be an interesting problem for heterogeneous migration..

Paul

[*] The most recent docs I have handy. Up to and including Core-2 Duo.