From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1Nq9QH-0004hS-IG for qemu-devel@nongnu.org; Fri, 12 Mar 2010 13:17:21 -0500 Received: from [199.232.76.173] (port=53506 helo=monty-python.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1Nq9QH-0004h0-4f for qemu-devel@nongnu.org; Fri, 12 Mar 2010 13:17:21 -0500 Received: from Debian-exim by monty-python.gnu.org with spam-scanned (Exim 4.60) (envelope-from ) id 1Nq9QG-0002EY-M7 for qemu-devel@nongnu.org; Fri, 12 Mar 2010 13:17:20 -0500 Received: from mx20.gnu.org ([199.232.41.8]:56014) by monty-python.gnu.org with esmtps (TLS-1.0:RSA_AES_256_CBC_SHA1:32) (Exim 4.60) (envelope-from ) id 1Nq9QG-0002ER-9I for qemu-devel@nongnu.org; Fri, 12 Mar 2010 13:17:20 -0500 Received: from mail.codesourcery.com ([38.113.113.100]) by mx20.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1Nq9QE-0003fi-Q8 for qemu-devel@nongnu.org; Fri, 12 Mar 2010 13:17:19 -0500 From: Paul Brook Subject: Re: [Qemu-devel] [PATCH QEMU] transparent hugepage support Date: Fri, 12 Mar 2010 18:17:05 +0000 References: <20100311151427.GE5677@random.random> <201003121710.54782.paul@codesourcery.com> <20100312174140.GV5677@random.random> In-Reply-To: <20100312174140.GV5677@random.random> MIME-Version: 1.0 Content-Type: Text/Plain; charset="iso-8859-1" Content-Transfer-Encoding: 7bit Message-Id: <201003121817.05524.paul@codesourcery.com> List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Andrea Arcangeli Cc: qemu-devel@nongnu.org, Avi Kivity > > No particular preference. Or you could have .../page_sizes list all > > available sizes, and have qemu take the first one (or last depending on > > sort order). > > That would also work. Considering that the current transparent > hugepage support won't support any more than 1 page, I think it's ok > to call it hpage_size, the fact that amd/intel will add a 64k page > size is purely hypothetical It's only hypothetical on x86. Many other architectures already support this (at least ARM, MIPS, IA64, SPARC). Paul