From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1NupbJ-0004Cu-EI for qemu-devel@nongnu.org; Thu, 25 Mar 2010 12:08:05 -0400 Received: from [140.186.70.92] (port=36978 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1NupbG-00049T-Th for qemu-devel@nongnu.org; Thu, 25 Mar 2010 12:08:04 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.69) (envelope-from ) id 1NupZX-0005nj-8g for qemu-devel@nongnu.org; Thu, 25 Mar 2010 12:06:19 -0400 Received: from mx20.gnu.org ([199.232.41.8]:50814) by eggs.gnu.org with esmtp (Exim 4.69) (envelope-from ) id 1NupZX-0005nQ-4O for qemu-devel@nongnu.org; Thu, 25 Mar 2010 12:06:15 -0400 Received: from mail.codesourcery.com ([38.113.113.100]) by mx20.gnu.org with esmtp (Exim 4.60) (envelope-from ) id 1NupZW-0004bq-2u for qemu-devel@nongnu.org; Thu, 25 Mar 2010 12:06:14 -0400 Date: Thu, 25 Mar 2010 09:06:12 -0700 From: Nathan Froyd Subject: Re: [Qemu-devel] [PATCH 09/10] target-alpha: Implement load-locked/store-conditional properly. Message-ID: <20100325160611.GU16726@codesourcery.com> References: <20100325133920.GS16726@codesourcery.com> <4BAB853E.1070303@twiddle.net> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <4BAB853E.1070303@twiddle.net> List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Richard Henderson Cc: qemu-devel@nongnu.org, aurelien@aurel32.net On Thu, Mar 25, 2010 at 08:46:06AM -0700, Richard Henderson wrote: > On 03/25/2010 06:39 AM, Nathan Froyd wrote: > > On Wed, Mar 24, 2010 at 05:11:43PM -0700, Richard Henderson wrote: > >> Use __sync_bool_compare_and_swap to yield correctly atomic results. > >> As yet, this assumes running on an strict-memory-ordering host (i.e. x86), > >> since we're still "implementing" the memory-barrier instructions as nops. > > > > Did the approach taken by other targets (arm/mips/ppc) not work on > > Alpha? > > Mips doesn't even pretend to be atomic. It pretends just as much as ppc and arm. See translate.c:OP_ST_ATOMIC. > Powerpc and Arm -- if I've got this straight -- use some sort of stop-the-world > mutex+condition and then perform the compare-and-exchange by hand. I can't > see how that's better than using an actual compare-and-exchange provided by > the host cpu. In fact, I'm mildly horrified by the prospect. Oh, I didn't say it was pretty. But it does work fairly well in practice--enough to pass most of glibc's NPTL testsuite, for instance. (The remaining cases are tricky things, like cross-process locks.) I think--though Paul would remember better than I--that the stop-the-world approach might have been taken due to a desire to continue compiling with gcc < 4.1. I don't know how much of a desdirata that still is. (stop-the-world is also somewhat less complex than the previous implementation, which involved page protection games.) Certainly using actual compare-and-exchange would be much faster. -Nathan