From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from mailman by lists.gnu.org with tmda-scanned (Exim 4.43) id 1Nz7Qh-0004NP-Ae for qemu-devel@nongnu.org; Tue, 06 Apr 2010 07:58:51 -0400 Received: from [140.186.70.92] (port=54826 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1Nz7Qg-0004ND-54 for qemu-devel@nongnu.org; Tue, 06 Apr 2010 07:58:51 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.69) (envelope-from ) id 1Nz7Qe-0001mY-4F for qemu-devel@nongnu.org; Tue, 06 Apr 2010 07:58:49 -0400 Received: from mx1.redhat.com ([209.132.183.28]:5700) by eggs.gnu.org with esmtp (Exim 4.69) (envelope-from ) id 1Nz7Qd-0001mP-Rn for qemu-devel@nongnu.org; Tue, 06 Apr 2010 07:58:48 -0400 Date: Tue, 6 Apr 2010 14:55:06 +0300 From: "Michael S. Tsirkin" Message-ID: <20100406115506.GA16539@redhat.com> References: <1270554249-24861-1-git-send-email-weil@mail.berlios.de> <1270554249-24861-10-git-send-email-weil@mail.berlios.de> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1270554249-24861-10-git-send-email-weil@mail.berlios.de> Subject: [Qemu-devel] Re: [PATCH 9/9] eepro100: Fix PCI interrupt pin configuration regression List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Stefan Weil Cc: QEMU Developers On Tue, Apr 06, 2010 at 01:44:09PM +0200, Stefan Weil wrote: > Commit 15e89f5916c9e82347cbd1fd416db3e348bab426 > removed this setting, but it is still needed. > > Without this patch, e100 device drivers using > interrupts don't work with qemu. > > See other nic emulations which also set the > PCI interrupt pin. > > Signed-off-by: Stefan Weil I actually misread the spec. We don't need the TODO either. I'll drop it. > --- > hw/eepro100.c | 4 ++++ > 1 files changed, 4 insertions(+), 0 deletions(-) > > diff --git a/hw/eepro100.c b/hw/eepro100.c > index 2401888..bc7e3f1 100644 > --- a/hw/eepro100.c > +++ b/hw/eepro100.c > @@ -475,6 +475,10 @@ static void e100_pci_reset(EEPRO100State * s, E100PCIDeviceInfo *e100_device) > /* PCI Latency Timer */ > pci_set_byte(pci_conf + PCI_LATENCY_TIMER, 0x20); /* latency timer = 32 clocks */ > /* Capability Pointer is set by PCI framework. */ > + /* Interrupt Line */ > + /* Interrupt Pin */ > + /* TODO: RST# value should be 0. */ > + pci_set_byte(pci_conf + PCI_INTERRUPT_PIN, 1); /* interrupt pin 0 */ > /* Minimum Grant */ > pci_set_byte(pci_conf + PCI_MIN_GNT, 0x08); > /* Maximum Latency */ > -- > 1.7.0