From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from [140.186.70.92] (port=53532 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1OFmJw-0003PE-0f for qemu-devel@nongnu.org; Sat, 22 May 2010 06:52:46 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.69) (envelope-from ) id 1OFmJu-0004Ql-Dn for qemu-devel@nongnu.org; Sat, 22 May 2010 06:52:43 -0400 Received: from mail-fx0-f45.google.com ([209.85.161.45]:45113) by eggs.gnu.org with esmtp (Exim 4.69) (envelope-from ) id 1OFmJu-0004M6-99 for qemu-devel@nongnu.org; Sat, 22 May 2010 06:52:42 -0400 Received: by mail-fx0-f45.google.com with SMTP id 14so550821fxm.4 for ; Sat, 22 May 2010 03:52:41 -0700 (PDT) Received: from localhost ([127.0.0.1] helo=[192.168.1.2]) by skyserv with esmtp (Exim 4.71) (envelope-from ) id 1OFmJs-0004p0-5R for qemu-devel@nongnu.org; Sat, 22 May 2010 14:52:40 +0400 From: "Igor V. Kovalenko" Date: Sat, 22 May 2010 14:52:40 +0400 Message-ID: <20100522105240.18257.19008.stgit@skyserv> In-Reply-To: <20100522104440.18257.92813.stgit@skyserv> References: <20100522104440.18257.92813.stgit@skyserv> MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: 7bit Subject: [Qemu-devel] [PATCH 5/5] sparc64: flush translations on mmu context change List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org From: Igor V. Kovalenko - two pairs of softmmu indexes bind softmmu tlb to cpu tlb in fault handlers using value of DMMU primary and secondary context registers, so we need to flush softmmu translations when context registers are changed Signed-off-by: Igor V. Kovalenko --- target-sparc/op_helper.c | 6 ++++++ 1 files changed, 6 insertions(+), 0 deletions(-) diff --git a/target-sparc/op_helper.c b/target-sparc/op_helper.c index 28224b2..edeeb44 100644 --- a/target-sparc/op_helper.c +++ b/target-sparc/op_helper.c @@ -2959,9 +2959,15 @@ void helper_st_asi(target_ulong addr, target_ulong val, int asi, int size) break; case 1: // Primary context env->dmmu.mmu_primary_context = val; + /* can be optimized to only flush MMU_USER_IDX + and MMU_KERNEL_IDX entries */ + tlb_flush(env, 1); break; case 2: // Secondary context env->dmmu.mmu_secondary_context = val; + /* can be optimized to only flush MMU_USER_SECONDARY_IDX + and MMU_KERNEL_SECONDARY_IDX entries */ + tlb_flush(env, 1); break; case 5: // TSB access DPRINTF_MMU("dmmu TSB write: 0x%016" PRIx64 " -> 0x%016"