From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from [140.186.70.92] (port=33635 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1OIh4l-0003NZ-C6 for qemu-devel@nongnu.org; Sun, 30 May 2010 07:53:08 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.69) (envelope-from ) id 1OIh4j-0000Se-EQ for qemu-devel@nongnu.org; Sun, 30 May 2010 07:53:07 -0400 Received: from mx1.redhat.com ([209.132.183.28]:10525) by eggs.gnu.org with esmtp (Exim 4.69) (envelope-from ) id 1OIh4j-0000SP-6u for qemu-devel@nongnu.org; Sun, 30 May 2010 07:53:05 -0400 Date: Sun, 30 May 2010 14:52:59 +0300 From: Gleb Natapov Subject: Re: [Qemu-devel] Re: [RFT][PATCH 07/15] qemu_irq: Add IRQ handlers with delivery feedback Message-ID: <20100530115259.GA24302@redhat.com> References: <20100528073135.GC17805@redhat.com> <20100528204746.GC3604@redhat.com> <20100529143857.GE3604@redhat.com> <20100529163235.GI3604@redhat.com> <20100530054143.GI5474@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Blue Swirl Cc: Jan Kiszka , qemu-devel@nongnu.org, Juan Quintela On Sun, May 30, 2010 at 11:41:36AM +0000, Blue Swirl wrote: > >> I meant that in the scenario, the guest won't change the RTC before > >> 30Mcyc because of some built in determinism in the guest. At that > >> point, because of some reason, the change would happen. > >> > > I still don't understand what are you trying to say here. Guest changes > > frequency because of some even in the guest. It is totally independent > > of what happens in QEMUs RTC emulation. > > I'm trying to understand the order of events. In the scenario, the > order of events on real HW would be: > 10Mcyc: tick IRQ 1 > 20Mcyc: tick IRQ 2 > 30Mcyc: tick IRQ 3 > 30Mcyc: reprogram timer > 31Mcyc: tick IRQ 4 > 32Mcyc: tick IRQ 5 > 33Mcyc: tick IRQ 6 > 34Mcyc: tick IRQ 7 > > With QEMU, the order could become: > 30Mcyc: reprogram timer > 30.5Mcyc: tick IRQ 1 > 31Mcyc: tick IRQ 2 > 31.5Mcyc: tick IRQ 3 > 32Mcyc: tick IRQ 4 > 32.5Mcyc: tick IRQ 5 > 33Mcyc: tick IRQ 6 > 34Mcyc: tick IRQ 7 > > Correct? Not sure, your description is not complete. Let me try: On real HW: 10Mcyc: tick IRQ 1 -> delivered to an OS 20Mcyc: tick IRQ 2 -> delivered to an OS 30Mcyc: tick IRQ 3 -> delivered to an OS 30Mcyc: reprogram timer 31Mcyc: tick IRQ 4 -> delivered to an OS 32Mcyc: tick IRQ 5 -> delivered to an OS 33Mcyc: tick IRQ 6 -> delivered to an OS 34Mcyc: tick IRQ 7 -> delivered to an OS With QEMU: 10Mcyc: tick IRQ 1 -> coalesced 20Mcyc: tick IRQ 2 -> coalesced 30Mcyc: tick IRQ 3 -> coalesced 30Mcyc: reprogram timer 30.1Mcyc: tick IRQ 1 -> delivered to an OS 30.2Mcyc: tick IRQ 2 -> delivered to an OS 30.3Mcyc: tick IRQ 3 -> delivered to an OS 31Mcyc: tick IRQ 4 -> delivered to an OS 32Mcyc: tick IRQ 5 -> delivered to an OS 33Mcyc: tick IRQ 6 -> delivered to an OS 34Mcyc: tick IRQ 7 -> delivered to an OS -- Gleb.