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From: "Igor V. Kovalenko" <igor.v.kovalenko@gmail.com>
To: qemu-devel@nongnu.org
Subject: [Qemu-devel] [PATCH 8/8] sparc64: fix umul and smul insns
Date: Wed, 02 Jun 2010 00:12:58 +0400	[thread overview]
Message-ID: <20100601201258.5908.86455.stgit@skyserv> (raw)
In-Reply-To: <20100601200434.5908.19495.stgit@skyserv>

From: Igor V. Kovalenko <igor.v.kovalenko@gmail.com>

- truncate and sign or zero extend operands before multiplication
- factor out common code to gen_op_multiply() with parameter to sign/zero extend
- call gen_op_multiply from gen_op_umul and gen_op_smul

Signed-off-by: Igor V. Kovalenko <igor.v.kovalenko@gmail.com>
---
 target-sparc/translate.c |   55 ++++++++++++++++++++++++----------------------
 1 files changed, 29 insertions(+), 26 deletions(-)

diff --git a/target-sparc/translate.c b/target-sparc/translate.c
index 0bc1a82..23f9519 100644
--- a/target-sparc/translate.c
+++ b/target-sparc/translate.c
@@ -662,50 +662,53 @@ static inline void gen_op_mulscc(TCGv dst, TCGv src1, TCGv src2)
     tcg_gen_mov_tl(dst, cpu_cc_dst);
 }
 
-static inline void gen_op_umul(TCGv dst, TCGv src1, TCGv src2)
+static inline void gen_op_multiply(TCGv dst, TCGv src1, TCGv src2, int sign_ext)
 {
+    TCGv_i32 r_src1, r_src2;
     TCGv_i64 r_temp, r_temp2;
 
+    r_src1 = tcg_temp_new_i32();
+    r_src2 = tcg_temp_new_i32();
+
+    tcg_gen_trunc_tl_i32(r_src1, src1);
+    tcg_gen_trunc_tl_i32(r_src2, src2);
+
     r_temp = tcg_temp_new_i64();
     r_temp2 = tcg_temp_new_i64();
 
-    tcg_gen_extu_tl_i64(r_temp, src2);
-    tcg_gen_extu_tl_i64(r_temp2, src1);
+    if (sign_ext) {
+        tcg_gen_ext_i32_i64(r_temp, r_src2);
+        tcg_gen_ext_i32_i64(r_temp2, r_src1);
+    } else {
+        tcg_gen_extu_i32_i64(r_temp, r_src2);
+        tcg_gen_extu_i32_i64(r_temp2, r_src1);
+    }
+
     tcg_gen_mul_i64(r_temp2, r_temp, r_temp2);
 
     tcg_gen_shri_i64(r_temp, r_temp2, 32);
     tcg_gen_trunc_i64_tl(cpu_tmp0, r_temp);
     tcg_temp_free_i64(r_temp);
     tcg_gen_andi_tl(cpu_y, cpu_tmp0, 0xffffffff);
-#ifdef TARGET_SPARC64
-    tcg_gen_mov_i64(dst, r_temp2);
-#else
+
     tcg_gen_trunc_i64_tl(dst, r_temp2);
-#endif
+
     tcg_temp_free_i64(r_temp2);
+
+    tcg_temp_free_i32(r_src1);
+    tcg_temp_free_i32(r_src2);
 }
 
-static inline void gen_op_smul(TCGv dst, TCGv src1, TCGv src2)
+static inline void gen_op_umul(TCGv dst, TCGv src1, TCGv src2)
 {
-    TCGv_i64 r_temp, r_temp2;
-
-    r_temp = tcg_temp_new_i64();
-    r_temp2 = tcg_temp_new_i64();
-
-    tcg_gen_ext_tl_i64(r_temp, src2);
-    tcg_gen_ext_tl_i64(r_temp2, src1);
-    tcg_gen_mul_i64(r_temp2, r_temp, r_temp2);
+    /* zero-extend truncated operands before multiplication */
+    gen_op_multiply(dst, src1, src2, 0);
+}
 
-    tcg_gen_shri_i64(r_temp, r_temp2, 32);
-    tcg_gen_trunc_i64_tl(cpu_tmp0, r_temp);
-    tcg_temp_free_i64(r_temp);
-    tcg_gen_andi_tl(cpu_y, cpu_tmp0, 0xffffffff);
-#ifdef TARGET_SPARC64
-    tcg_gen_mov_i64(dst, r_temp2);
-#else
-    tcg_gen_trunc_i64_tl(dst, r_temp2);
-#endif
-    tcg_temp_free_i64(r_temp2);
+static inline void gen_op_smul(TCGv dst, TCGv src1, TCGv src2)
+{
+    /* sign-extend truncated operands before multiplication */
+    gen_op_multiply(dst, src1, src2, 1);
 }
 
 #ifdef TARGET_SPARC64

  parent reply	other threads:[~2010-06-01 20:13 UTC|newest]

Thread overview: 28+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2010-06-01 20:12 [Qemu-devel] [PATCH 0/8] sparc64 fixes Igor V. Kovalenko
2010-06-01 20:12 ` [Qemu-devel] [PATCH 1/8] sparc64: fix tag access register on mmu traps Igor V. Kovalenko
2010-06-01 20:12 ` [Qemu-devel] [PATCH 2/8] sparc64: fix missing address masking Igor V. Kovalenko
2010-06-01 20:44   ` Richard Henderson
2010-06-02  4:29     ` Igor Kovalenko
2010-06-02 13:47       ` Richard Henderson
2010-06-02 16:10         ` Blue Swirl
2010-06-02 16:46           ` Andreas Färber
2010-06-02 18:21             ` Igor Kovalenko
2010-06-02 19:20         ` Igor Kovalenko
2010-06-01 20:12 ` [Qemu-devel] [PATCH 3/8] sparc64: fix 32bit load sign extension Igor V. Kovalenko
2010-06-03 13:18   ` [Qemu-devel] " Paolo Bonzini
2010-06-03 15:25     ` Alexander Graf
2010-06-03 15:42       ` Paolo Bonzini
2010-06-03 19:59         ` Igor Kovalenko
2010-06-04  7:53           ` Paolo Bonzini
2010-06-04 10:18             ` Paolo Bonzini
2010-06-04 14:27               ` [Qemu-devel] [PATCH] target-i386: fix decoding of negative 4-byte displacements Paolo Bonzini
2010-06-04 16:23                 ` Richard Henderson
2010-06-04 20:03                   ` Blue Swirl
2010-06-01 20:12 ` [Qemu-devel] [PATCH 4/8] sparc64: fix ldxfsr insn Igor V. Kovalenko
2010-06-01 20:12 ` [Qemu-devel] [PATCH 5/8] sparc64: use symbolic name for MMU index Igor V. Kovalenko
2010-06-02 16:16   ` Blue Swirl
2010-06-02 18:45     ` Igor Kovalenko
2010-06-01 20:12 ` [Qemu-devel] [PATCH 6/8] sparc64: improve ldf and stf insns Igor V. Kovalenko
2010-06-01 20:12 ` [Qemu-devel] [PATCH 7/8] sparc64: fix udiv and sdiv insns Igor V. Kovalenko
2010-06-01 20:12 ` Igor V. Kovalenko [this message]
2010-06-02 20:27 ` [Qemu-devel] [PATCH 0/8] sparc64 fixes Blue Swirl

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