qemu-devel.nongnu.org archive mirror
 help / color / mirror / Atom feed
From: Nathan Froyd <froydnj@codesourcery.com>
To: Richard Henderson <rth@twiddle.net>
Cc: qemu-devel@nongnu.org, aurelien@aurel32.net
Subject: Re: [Qemu-devel] [PATCH 06/10] target-mips: add microMIPS ASE support
Date: Fri, 4 Jun 2010 11:48:07 -0700	[thread overview]
Message-ID: <20100604184806.GH19235@codesourcery.com> (raw)
In-Reply-To: <4C09464E.3040102@twiddle.net>

On Fri, Jun 04, 2010 at 11:30:38AM -0700, Richard Henderson wrote:
> On 05/24/2010 09:19 AM, Nathan Froyd wrote:
> > +    int (*ldfun)(target_ulong);
> > +
> > +    switch (mem_idx)
> > +    {
> > +    case 0: ldfun = ldl_kernel; break;
> > +    case 1: ldfun = ldl_super; break;
> > +    default:
> > +    case 2: ldfun = ldl_user; break;
> > +    }
> 
> This *should* now be a compile error.  The return type should
> now be "uint32_t", not "int".

Will fix, thanks for pointing that out.

> > @@ -2535,26 +2555,29 @@ static void gen_compute_branch (DisasContext *ctx, uint32_t opc,
> >          case OPC_JALX:
> >              ctx->hflags |= MIPS_HFLAG_BX;
> >              /* Fallthrough */
> > +        case OPC_JALS:
> >          case OPC_JAL:
> >              blink = 31;
> >              ctx->hflags |= MIPS_HFLAG_B;
> > -            ctx->hflags |= (ctx->hflags & MIPS_HFLAG_M16
> > +            ctx->hflags |= (opc == OPC_JALS
> >                              ? MIPS_HFLAG_BDS16
> >                              : MIPS_HFLAG_BDS32);
> 
> Changed semantics here?  You're no longer testing M16 bit.
> Or is that later handled by switching mips16 to JALS too?

It ought to be handled by switching mips16 to use JALS.  I see that I
didn't do that.

> And if so, perhaps this patch should be broken into two, where
> you introduce the new opcodes and hflags changes and apply them
> as-needed to the mips16 code.  Thus one can verify that the
> semantics for mips16 are the same before and after.

I don't think there are any hflags changes, but the point is
well-taken.  I'll do that.

> > +    if (base == 0) {
> > +        tcg_gen_movi_tl(t0, 0);
> > +    } else {
> > +        gen_load_gpr(t0, base);
> > +    }
> 
> gen_load_gpr already takes care of R0.

Will fix.

> > +#if 0
> > +    case 0x01:
> > +        switch (minor) {
> > +        case MFHI_ACC:
> > +            gen_HILO(ctx, OPC_MFHI, rs);
> 
> New if 0 code?

Yup, will delete.

-Nathan

  reply	other threads:[~2010-06-04 18:48 UTC|newest]

Thread overview: 30+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2010-05-24 16:19 [Qemu-devel] [PATCH 00/10] target-mips: add microMIPS ASE support, v2 Nathan Froyd
2010-05-24 16:19 ` [Qemu-devel] [PATCH 01/10] target-mips: break out [ls][wd]c1 and rdhwr insn generation Nathan Froyd
2010-06-04 17:47   ` Richard Henderson
2010-06-08 17:48   ` Aurelien Jarno
2010-05-24 16:19 ` [Qemu-devel] [PATCH 02/10] target-mips: add microMIPS-specific bits to mips-defs.h Nathan Froyd
2010-06-04 17:51   ` Richard Henderson
2010-05-24 16:19 ` [Qemu-devel] [PATCH 03/10] target-mips: add enum constants for various invocations of FOP Nathan Froyd
2010-06-04 17:45   ` Richard Henderson
2010-06-04 17:50     ` Nathan Froyd
2010-06-04 18:31       ` Richard Henderson
2010-05-24 16:19 ` [Qemu-devel] [PATCH 04/10] target-mips: refactor {c, abs}.cond.fmt insns Nathan Froyd
2010-06-04 18:01   ` Richard Henderson
2010-05-24 16:19 ` [Qemu-devel] [PATCH 05/10] target-mips: small changes to use new FMT_ enums Nathan Froyd
2010-06-04 18:02   ` Richard Henderson
2010-05-24 16:19 ` [Qemu-devel] [PATCH 06/10] target-mips: add microMIPS ASE support Nathan Froyd
2010-06-04 18:30   ` Richard Henderson
2010-06-04 18:48     ` Nathan Froyd [this message]
2010-05-24 16:19 ` [Qemu-devel] [PATCH 07/10] target-mips: add microMIPS CPUs Nathan Froyd
2010-06-04 18:35   ` Richard Henderson
2010-06-04 18:50     ` Nathan Froyd
2010-05-24 16:19 ` [Qemu-devel] [PATCH 08/10] target-mips: add microMIPS exception handler support Nathan Froyd
2010-06-04 18:33   ` Richard Henderson
2010-05-24 16:19 ` [Qemu-devel] [PATCH 09/10] linux-user: honor low bit of entry PC for MIPS Nathan Froyd
2010-06-04 18:36   ` Richard Henderson
2010-05-24 16:19 ` [Qemu-devel] [PATCH 10/10] hw: honor low bit in mipssim machine Nathan Froyd
2010-06-04 18:37   ` Richard Henderson
2010-06-04 15:51 ` [Qemu-devel] [PATCH 00/10] target-mips: add microMIPS ASE support, v2 Nathan Froyd
2010-06-04 17:26   ` Aurelien Jarno
2010-06-04 17:50 ` Richard Henderson
  -- strict thread matches above, loose matches on Subject: below --
2010-05-20 14:52 [Qemu-devel] [PATCH 00/10] target-mips: add microMIPS ASE support Nathan Froyd
2010-05-20 14:52 ` [Qemu-devel] [PATCH 06/10] " Nathan Froyd

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20100604184806.GH19235@codesourcery.com \
    --to=froydnj@codesourcery.com \
    --cc=aurelien@aurel32.net \
    --cc=qemu-devel@nongnu.org \
    --cc=rth@twiddle.net \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).