From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from [140.186.70.92] (port=46335 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1OKbwA-0000sp-PD for qemu-devel@nongnu.org; Fri, 04 Jun 2010 14:48:12 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.69) (envelope-from ) id 1OKbw9-0006LK-5d for qemu-devel@nongnu.org; Fri, 04 Jun 2010 14:48:10 -0400 Received: from mail.codesourcery.com ([38.113.113.100]:37969) by eggs.gnu.org with esmtp (Exim 4.69) (envelope-from ) id 1OKbw8-0006L3-RV for qemu-devel@nongnu.org; Fri, 04 Jun 2010 14:48:09 -0400 Date: Fri, 4 Jun 2010 11:48:07 -0700 From: Nathan Froyd Subject: Re: [Qemu-devel] [PATCH 06/10] target-mips: add microMIPS ASE support Message-ID: <20100604184806.GH19235@codesourcery.com> References: <1274717984-25887-1-git-send-email-froydnj@codesourcery.com> <1274717984-25887-7-git-send-email-froydnj@codesourcery.com> <4C09464E.3040102@twiddle.net> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <4C09464E.3040102@twiddle.net> List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Richard Henderson Cc: qemu-devel@nongnu.org, aurelien@aurel32.net On Fri, Jun 04, 2010 at 11:30:38AM -0700, Richard Henderson wrote: > On 05/24/2010 09:19 AM, Nathan Froyd wrote: > > + int (*ldfun)(target_ulong); > > + > > + switch (mem_idx) > > + { > > + case 0: ldfun = ldl_kernel; break; > > + case 1: ldfun = ldl_super; break; > > + default: > > + case 2: ldfun = ldl_user; break; > > + } > > This *should* now be a compile error. The return type should > now be "uint32_t", not "int". Will fix, thanks for pointing that out. > > @@ -2535,26 +2555,29 @@ static void gen_compute_branch (DisasContext *ctx, uint32_t opc, > > case OPC_JALX: > > ctx->hflags |= MIPS_HFLAG_BX; > > /* Fallthrough */ > > + case OPC_JALS: > > case OPC_JAL: > > blink = 31; > > ctx->hflags |= MIPS_HFLAG_B; > > - ctx->hflags |= (ctx->hflags & MIPS_HFLAG_M16 > > + ctx->hflags |= (opc == OPC_JALS > > ? MIPS_HFLAG_BDS16 > > : MIPS_HFLAG_BDS32); > > Changed semantics here? You're no longer testing M16 bit. > Or is that later handled by switching mips16 to JALS too? It ought to be handled by switching mips16 to use JALS. I see that I didn't do that. > And if so, perhaps this patch should be broken into two, where > you introduce the new opcodes and hflags changes and apply them > as-needed to the mips16 code. Thus one can verify that the > semantics for mips16 are the same before and after. I don't think there are any hflags changes, but the point is well-taken. I'll do that. > > + if (base == 0) { > > + tcg_gen_movi_tl(t0, 0); > > + } else { > > + gen_load_gpr(t0, base); > > + } > > gen_load_gpr already takes care of R0. Will fix. > > +#if 0 > > + case 0x01: > > + switch (minor) { > > + case MFHI_ACC: > > + gen_HILO(ctx, OPC_MFHI, rs); > > New if 0 code? Yup, will delete. -Nathan