From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from [140.186.70.92] (port=56321 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1OMUAY-0001GB-EK for qemu-devel@nongnu.org; Wed, 09 Jun 2010 18:54:48 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.69) (envelope-from ) id 1OMUAQ-00012h-Ta for qemu-devel@nongnu.org; Wed, 09 Jun 2010 18:54:40 -0400 Received: from hall.aurel32.net ([88.191.82.174]:58650) by eggs.gnu.org with esmtp (Exim 4.69) (envelope-from ) id 1OMUAQ-00012d-PE for qemu-devel@nongnu.org; Wed, 09 Jun 2010 18:54:38 -0400 Date: Thu, 10 Jun 2010 00:54:36 +0200 From: Aurelien Jarno Subject: Re: [Qemu-devel] [PATCH 04/35] tcg-s390: Compute is_write in cpu_signal_handler. Message-ID: <20100609225436.GH3008@ohm.aurel32.net> References: <1275678883-7082-1-git-send-email-rth@twiddle.net> <1275678883-7082-5-git-send-email-rth@twiddle.net> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-15 Content-Disposition: inline In-Reply-To: <1275678883-7082-5-git-send-email-rth@twiddle.net> List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Richard Henderson Cc: qemu-devel@nongnu.org, agraf@suse.de On Fri, Jun 04, 2010 at 12:14:12PM -0700, Richard Henderson wrote: > Signed-off-by: Richard Henderson > --- > cpu-exec.c | 42 +++++++++++++++++++++++++++++++++++++++--- > 1 files changed, 39 insertions(+), 3 deletions(-) Thanks, applied. > diff --git a/cpu-exec.c b/cpu-exec.c > index c776605..026980a 100644 > --- a/cpu-exec.c > +++ b/cpu-exec.c > @@ -1156,11 +1156,47 @@ int cpu_signal_handler(int host_signum, void *pinfo, > siginfo_t *info = pinfo; > struct ucontext *uc = puc; > unsigned long pc; > - int is_write; > + uint16_t *pinsn; > + int is_write = 0; > > pc = uc->uc_mcontext.psw.addr; > - /* XXX: compute is_write */ > - is_write = 0; > + > + /* ??? On linux, the non-rt signal handler has 4 (!) arguments instead > + of the normal 2 arguments. The 3rd argument contains the "int_code" > + from the hardware which does in fact contain the is_write value. > + The rt signal handler, as far as I can tell, does not give this value > + at all. Not that we could get to it from here even if it were. */ > + /* ??? This is not even close to complete, since it ignores all > + of the read-modify-write instructions. */ > + pinsn = (uint16_t *)pc; > + switch (pinsn[0] >> 8) { > + case 0x50: /* ST */ > + case 0x42: /* STC */ > + case 0x40: /* STH */ > + is_write = 1; > + break; > + case 0xc4: /* RIL format insns */ > + switch (pinsn[0] & 0xf) { > + case 0xf: /* STRL */ > + case 0xb: /* STGRL */ > + case 0x7: /* STHRL */ > + is_write = 1; > + } > + break; > + case 0xe3: /* RXY format insns */ > + switch (pinsn[2] & 0xff) { > + case 0x50: /* STY */ > + case 0x24: /* STG */ > + case 0x72: /* STCY */ > + case 0x70: /* STHY */ > + case 0x8e: /* STPQ */ > + case 0x3f: /* STRVH */ > + case 0x3e: /* STRV */ > + case 0x2f: /* STRVG */ > + is_write = 1; > + } > + break; > + } > return handle_cpu_signal(pc, (unsigned long)info->si_addr, > is_write, &uc->uc_sigmask, puc); > } > -- > 1.7.0.1 > > > -- Aurelien Jarno GPG: 1024D/F1BCDB73 aurelien@aurel32.net http://www.aurel32.net