Re: [Qemu-devel] [PATCH 09/16] Enable message delivery via IRQs

[Paul Brook <paul@codesourcery.com>]

> >> For the memory access case, in practice the interface could be
> >> sysbus_memory_rw(DeviceState *parent, target_phys_addr_t addr,
> >> target_phys_addr_t size)
> > 
> > Why "parent"?
> 
> Parent device or bus host bridge device. Alternatively there could be
> a bus handle.

A device has no way of knowing where that bust host bridge is, and this may be 
the wrong device anyway. The access may be directed at another device on the 
same bus.  A bus handle is trivial to derive this from the device itself.

> > I don't see any point point trying to squeeze this through a common
> > message passing API. We *could* do that if we really wanted, but It's a
> > lot of hassle. If devices are going to end up using wrappers that look a
> > lot like a straight API then what's the point?
> 
> Without IRQ and other messages, I agree that at this point it would
> not make much sense. Do you think this API as straight implementation
> would work? Compared to previous attempts for Generic DMA, we'd avoid
> any IO vector splitting/reallocations etc.

We have already merged a "generic DMA" infrastructure 
(cpu_physical_memory_map). See also dma-helpers.c for code that uses this to 
implement zero-copy transfers to/from block devices.

This is missing code to allow manipulation by intermediate bus/bridges, but I 
believe the basic API is fairly sound. Addition of a device handle or error 
reporting should be possible without requiring major changes to the device 
code.

Paul