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Date: Wed, 7 Jul 2010 20:36:20 +0300
From: "Michael S. Tsirkin" <mst@redhat.com>
Subject: Re: [Qemu-devel] [PATCH] pci: pass bridge update to secondary bus
Message-ID: <20100707173620.GB15597@redhat.com>
References: <20100706112327.GA20108@redhat.com>
	<AANLkTin_vG_LSIXf8AnE61-va8XiUydx6rAfnK-VJT4i@mail.gmail.com>
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To: Blue Swirl <blauwirbel@gmail.com>
Cc: yamahata@valinux.co.jp, qemu-devel@nongnu.org

On Wed, Jul 07, 2010 at 05:31:39PM +0000, Blue Swirl wrote:
> On Tue, Jul 6, 2010 at 11:23 AM, Michael S. Tsirkin <mst@redhat.com> wr=
ote:
> > bridge config write should trigger updates
> > on the secondary bus. never on the primary bus.
>=20
> If this is true, shouldn't updates happen on all buses from secondary
> to subordinate? Do we know which of these are immediately below
> primary bus?

pci_bridge_update_mappings does this already.

> >
> > Signed-off-by: Michael S. Tsirkin <mst@redhat.com>
> > ---
> >
> > Compile-tested only.
> > Isaku Yamahata, could you review this please?
> > You wrote the code, and you seem to have some bridged setups.
> >
> > =A0hw/pci.c | =A0 =A04 +++-
> > =A01 files changed, 3 insertions(+), 1 deletions(-)
> >
> > diff --git a/hw/pci.c b/hw/pci.c
> > index 926cf63..011d83e 100644
> > --- a/hw/pci.c
> > +++ b/hw/pci.c
> > @@ -1513,7 +1513,9 @@ static void pci_bridge_write_config(PCIDevice *=
d,
> > =A0 =A0 =A0 =A0 /* memory base/limit, prefetchable base/limit and
> > =A0 =A0 =A0 =A0 =A0 =A0io base/limit upper 16 */
> > =A0 =A0 =A0 =A0 ranges_overlap(address, len, PCI_MEMORY_BASE, 20)) {
> > - =A0 =A0 =A0 =A0pci_bridge_update_mappings(d->bus);
> > + =A0 =A0 =A0 =A0PCIBridge *s =3D container_of(d, PCIBridge, dev);
> > + =A0 =A0 =A0 =A0PCIBus *secondary_bus =3D &s->bus;
> > + =A0 =A0 =A0 =A0pci_bridge_update_mappings(secondary_bus);
> > =A0 =A0 }
> > =A0}
> >
> > --
> > 1.7.2.rc0.14.g41c1c
> >
> >