From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from [140.186.70.92] (port=46113 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1Ob39J-0003GD-L3 for qemu-devel@nongnu.org; Mon, 19 Jul 2010 23:05:42 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.69) (envelope-from ) id 1Ob39H-0000KQ-ID for qemu-devel@nongnu.org; Mon, 19 Jul 2010 23:05:41 -0400 Received: from mail-qw0-f45.google.com ([209.85.216.45]:39059) by eggs.gnu.org with esmtp (Exim 4.69) (envelope-from ) id 1Ob39H-0000KH-G6 for qemu-devel@nongnu.org; Mon, 19 Jul 2010 23:05:39 -0400 Received: by qwf6 with SMTP id 6so2107484qwf.4 for ; Mon, 19 Jul 2010 20:05:38 -0700 (PDT) Date: Mon, 19 Jul 2010 23:05:34 -0400 From: Kevin O'Connor Message-ID: <20100720030534.GA6840@morn.localdomain> References: <33930ae88cd814000d782f802b962961a9bbad31.1278935094.git.yamahata@valinux.co.jp> <20100713005914.GB13722@morn.localdomain> <20100713094500.GF31689@valinux.co.jp> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20100713094500.GF31689@valinux.co.jp> Subject: [Qemu-devel] Re: [SeaBIOS] [PATCH 2/7] seabios: shadow: make device finding more generic. List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Isaku Yamahata Cc: seabios@seabios.org, qemu-devel@nongnu.org On Tue, Jul 13, 2010 at 06:45:00PM +0900, Isaku Yamahata wrote: > On Mon, Jul 12, 2010 at 08:59:14PM -0400, Kevin O'Connor wrote: > > On Mon, Jul 12, 2010 at 08:47:47PM +0900, Isaku Yamahata wrote: > > > pam register offset is north bridge specific. > > > So determine the offset based on found north bridge. > > > > Is it really just the offset that is north bridge specific? I thought > > the entire process was very north bridge specific. > > > > If so, I don't think it makes sense to pass back the pam0 register - > > instead the north bridge specific code should do the necessary work > > (using helper functions if possible). > > > > I have the same concern with part 3 and 4 of this series. > > I440fx and Q35 (all Intel chipset?) are similar in registers > which seabios programs, so I choice to abstract it at register offset level. > I don't expect that other vendor's chipset support is wanted. Although it isn't currently used, the memory locking support is useful on real machines too. I'd prefer a solution that would work on both qemu and real machines. It's minor for part 2 of the series, but I found part 3/4 to be hard to follow due to the way the flow of code jumps between machine specific code in dev-i440fx.c and the smm code in smm.c. > If you want more high level abstract, I'll respin the patch set. I've been meaning to look through the full series of changes in your repo, but have not yet had a chance to do so. I hope to get to that in the next few days. Sorry for the delay. -Kevin