From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from [140.186.70.92] (port=38674 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1OfDoK-0001q2-AC for qemu-devel@nongnu.org; Sat, 31 Jul 2010 11:17:17 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.69) (envelope-from ) id 1OfDoJ-0007CR-8G for qemu-devel@nongnu.org; Sat, 31 Jul 2010 11:17:16 -0400 Received: from hall.aurel32.net ([88.191.82.174]:55882) by eggs.gnu.org with esmtp (Exim 4.69) (envelope-from ) id 1OfDoJ-0007CM-2Z for qemu-devel@nongnu.org; Sat, 31 Jul 2010 11:17:15 -0400 Date: Sat, 31 Jul 2010 17:17:13 +0200 From: Aurelien Jarno Subject: Re: [Qemu-devel] [PATCH] [MIPS] Correctly identify multiple cpus in SMP systems Message-ID: <20100731151713.GJ20459@volta.aurel32.net> References: <1280572143-7474-1-git-send-email-hpoussin@reactos.org> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-15 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <1280572143-7474-1-git-send-email-hpoussin@reactos.org> List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: =?iso-8859-15?Q?Herv=E9?= Poussineau Cc: qemu-devel@nongnu.org On Sat, Jul 31, 2010 at 12:29:03PM +0200, Hervé Poussineau wrote: > > Signed-off-by: Hervé Poussineau > --- > target-mips/op_helper.c | 3 +-- > target-mips/translate.c | 3 +-- > 2 files changed, 2 insertions(+), 4 deletions(-) Thanks, applied. > diff --git a/target-mips/op_helper.c b/target-mips/op_helper.c > index a619b72..50c65bd 100644 > --- a/target-mips/op_helper.c > +++ b/target-mips/op_helper.c > @@ -1359,8 +1359,7 @@ void helper_mtc0_cause (target_ulong arg1) > void helper_mtc0_ebase (target_ulong arg1) > { > /* vectored interrupts not implemented */ > - /* Multi-CPU not implemented */ > - env->CP0_EBase = 0x80000000 | (arg1 & 0x3FFFF000); > + env->CP0_EBase = (env->CP0_EBase & ~0x3FFFF000) | (arg1 & 0x3FFFF000); > } > > void helper_mtc0_config0 (target_ulong arg1) > diff --git a/target-mips/translate.c b/target-mips/translate.c > index 6c72dee..20b66a8 100644 > --- a/target-mips/translate.c > +++ b/target-mips/translate.c > @@ -12679,8 +12679,7 @@ void cpu_reset (CPUMIPSState *env) > env->CP0_Random = env->tlb->nb_tlb - 1; > env->tlb->tlb_in_use = env->tlb->nb_tlb; > env->CP0_Wired = 0; > - /* SMP not implemented */ > - env->CP0_EBase = 0x80000000; > + env->CP0_EBase = 0x80000000 | (env->cpu_index & 0x3FF); > env->CP0_Status = (1 << CP0St_BEV) | (1 << CP0St_ERL); > /* vectored interrupts not implemented, timer on int 7, > no performance counters. */ > -- > 1.7.1.GIT > > > -- Aurelien Jarno GPG: 1024D/F1BCDB73 aurelien@aurel32.net http://www.aurel32.net