[Qemu-devel] Implementing atomic SWP in qemu-arm

[Qemu-devel] Implementing atomic SWP in qemu-arm

[Peter W Schultz]

It is my job to make qemu-arm implement the SWPcc instruction
atomically. Currently, qemu implements this instruction as a load
followed by a store, in a way vulnerable to race conditions.

We are extending qemu to handle a high number of processors, and our
simple testcase using pthreads seems to cause a deadlock somewhere in
qemu. It is the beliefs of my professor and I that the implementation
of SWP is the reason.

How would I go about modifying the qemu source to implement SWP
atomically? I have been studying the source for a few days now, and I
am at a loss as to what all needs to be done.

I feel it would be most desirable to add a TCG_SWAP instruction that
is guaranteed to be an atomic compare-and-swap, and implement that as
needed.

Best,
Kaedenn

-- 
Undergraduate Student
University of California, Santa Cruz

Re: [Qemu-devel] Implementing atomic SWP in qemu-arm

[Nathan Froyd]

On Wed, Aug 18, 2010 at 12:15:09PM -0700, Peter W Schultz wrote:
> How would I go about modifying the qemu source to implement SWP
> atomically? I have been studying the source for a few days now, and I
> am at a loss as to what all needs to be done.

You should look at how the load/store-exclusive instructions work and
see if you can use a similar mechanism.  It should be fairly
straightforward.

> I feel it would be most desirable to add a TCG_SWAP instruction that
> is guaranteed to be an atomic compare-and-swap, and implement that as
> needed.

I believe there was an thread several months ago discussing doing this
or something similar and it was decided that mechanism was not the way
to go.

-Nathan