From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from [140.186.70.92] (port=59879 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1Ot1rJ-0000Mz-Hu for qemu-devel@nongnu.org; Tue, 07 Sep 2010 13:21:30 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.69) (envelope-from ) id 1Ot1rF-00040j-Qh for qemu-devel@nongnu.org; Tue, 07 Sep 2010 13:21:22 -0400 Received: from mx1.redhat.com ([209.132.183.28]:47659) by eggs.gnu.org with esmtp (Exim 4.69) (envelope-from ) id 1Ot1rF-00040a-KV for qemu-devel@nongnu.org; Tue, 07 Sep 2010 13:21:21 -0400 Date: Tue, 7 Sep 2010 20:14:49 +0300 From: "Michael S. Tsirkin" Message-ID: <20100907171449.GA18374@redhat.com> References: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Subject: [Qemu-devel] Re: [PATCH 00/14] pcie port switch emulators List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Isaku Yamahata Cc: skandasa@cisco.com, adhyas@gmail.com, etmartin@cisco.com, qemu-devel@nongnu.org, wexu2@cisco.com On Mon, Sep 06, 2010 at 04:46:14PM +0900, Isaku Yamahata wrote: > This patch series implements pcie port switch emulators > which is basic part for pcie/q35 support. > This is for mst/pci tree. > > some random comments > - pci bus reset > As Anthony is cleaning up qdev reset stuff, so pci bus reset code > is commented out. Once the qdev clean up is done, the patch that > enabled pci bus reset will be sent. > > - vid/did > there are arbitrariness for pcie port switch. I just choose > Intel and IT one to model them. > > thanks, > > Isaku Yamahata (14): > RESEND apb: fix typo. > pci: consolidate pci_add_capability_at_offset() into > pci_add_capability(). > pci bridge: add helper function for ssvid capability. > pci: call hotplug callback even when not hotplug case for later use. > pci: make pci_parse_devfn() aware of func. > pci_ids.h: add vendor id of Texus Intesruments. OK, I pushed the above to the pci branch, and folded the first patch into the previous one. Didn't have time to test it yet, but I thought I'd push it out already to reduce mailing-list churn. > msi: implemented msi. I went over this and posted some comments. > pcie: helper functions for pcie extended capability. > pcie port: define struct PCIEPort/PCIESlot and helper functions > pcie root port: implement pcie root port. > pcie upstream port: pci express switch upstream port. > pcie downstream port: pci express switch downstream port. > pcie/hotplug: glue pushing attention button command. pcie_abp > pcie/aer: glue aer error injection into qemu monitor. Haven't reviewed the above yet. Are there bits that don't depend on msi? > Makefile.objs | 6 +- > hw/acpi_piix4.c | 3 + > hw/apb_pci.c | 6 +- > hw/eepro100.c | 4 +- > hw/msi.c | 362 +++++++++++ > hw/msi.h | 41 ++ > hw/msix.c | 3 +- > hw/pci.c | 70 ++- > hw/pci.h | 36 +- > hw/pci_bridge.c | 19 + > hw/pci_bridge.h | 3 + > hw/pci_ids.h | 2 + > hw/pcie.c | 1753 ++++++++++++++++++++++++++++++++++++++++++++++++++ > hw/pcie.h | 186 ++++++ > hw/pcie_downstream.c | 224 +++++++ > hw/pcie_downstream.h | 33 + > hw/pcie_port.c | 188 ++++++ > hw/pcie_port.h | 51 ++ > hw/pcie_root.c | 247 +++++++ > hw/pcie_root.h | 32 + > hw/pcie_upstream.c | 206 ++++++ > hw/pcie_upstream.h | 32 + > qemu-common.h | 3 + > qemu-monitor.hx | 36 + > sysemu.h | 9 + > 25 files changed, 3520 insertions(+), 35 deletions(-) > create mode 100644 hw/msi.c > create mode 100644 hw/msi.h > create mode 100644 hw/pcie.c > create mode 100644 hw/pcie.h > create mode 100644 hw/pcie_downstream.c > create mode 100644 hw/pcie_downstream.h > create mode 100644 hw/pcie_port.c > create mode 100644 hw/pcie_port.h > create mode 100644 hw/pcie_root.c > create mode 100644 hw/pcie_root.h > create mode 100644 hw/pcie_upstream.c > create mode 100644 hw/pcie_upstream.h