[Qemu-devel] [PATCH] target-ppc: clear MSR_POW on interrupt

[Thomas Monjalon <thomas.monjalon@openwide.fr>]

From: till <608107@bugs.launchpad.net>

According to FreeScale's 'Programming Environments Manual for 32-bit
Implementations of the PowerPC Architecture' [MPCFPE32B, Rev.3, 9/2005],
section 6.5, table 6-7, an interrupt resets MSR_POW to zero but qemu-0.12.4
fails to do so.
Resetting the bit is necessary in order to bring the processor out of power
management since otherwise it goes to sleep right away in the exception
handler, i.e., it is impossible to leave PM-mode.

https://bugs.launchpad.net/qemu/+bug/608107

Signed-off-by: till <608107@bugs.launchpad.net>
Acked-by: Thomas Monjalon <thomas@monjalon.net>

---
 target-ppc/helper.c |    1 +
 1 files changed, 1 insertions(+), 0 deletions(-)

diff --git a/target-ppc/helper.c b/target-ppc/helper.c
index f66fb30..0bb353e 100644
--- a/target-ppc/helper.c
+++ b/target-ppc/helper.c
@@ -2578,6 +2578,7 @@ static inline void powerpc_excp(CPUState *env, int excp_model, int excp)
     if (new_msr & ((1 << MSR_IR) | (1 << MSR_DR)))
         tlb_flush(env, 1);
     /* reload MSR with correct bits */
+    new_msr &= ~((target_ulong)1 << MSR_POW);
     new_msr &= ~((target_ulong)1 << MSR_EE);
     new_msr &= ~((target_ulong)1 << MSR_PR);
     new_msr &= ~((target_ulong)1 << MSR_FP);