[Qemu-devel] Re: [PATCH 0/2] PowerPC fixes

["Edgar E. Iglesias" <edgar.iglesias@gmail.com>]

On Sat, Sep 11, 2010 at 12:30:50PM +0200, Alexander Graf wrote:
> 
> On 11.09.2010, at 09:12, Edgar E. Iglesias wrote:
> 
> > On Sat, Sep 11, 2010 at 03:08:32AM +0200, Alexander Graf wrote:
> >> There goes another round of PowerPC fixes. Originally this should only have
> >> been a fix for the MSR_POW issue (bug 608107), but I also stumbed over recent
> >> Linux kernels not booting in qemu-system-ppc64. So a fix for that is also
> >> included.
> >> 
> >> With this new logic I didn't really took care of all HV corner cases, but HV
> >> mode is not properly implemented anyways (read: we should probably rip it out
> >> or do it properly, whichever is easier). I'm also fairly sure that the way
> >> things are now BookE doesn't work at all, so things again haven't become worse.
> >> 
> >> Alexander Graf (2):
> >>  PPC: Enable hint bits for lwarx/ldarx
> >>  PPC: Redesign interrupt trigger path
> > 
> > 
> > FWIW the MSR parts look good to me.
> > Also, none of this seems to break anything on my Virtex5 PPC-440 BookE
> > board (Im working on cleaning that up so it eventually can be submitted).
> 
> You have a working 440 MMU implementation?

I wouldnt say that :) I did some hacks in collaboration with Petalogix to
get some virtex4 (ppc-405) and virtex5 (ppc-440) designs to boot linux on
QEMU. The 440 was a bit problematic. I only did the bare minimum to
make linux happy and the patches are a quite hacky and spread out.

There is probably alot missing to accurately emulate a real 440, but it's
good enough to boot linux into user-space and run OK.

>FWIW on 440 (which is BookE) the whole interrupt stuff works differently, giving two different registers for status bits and saved MSR. Have you changed any bits there?

Nope, most of the changes are in the MMU model and some in the hw/ppc* parts.

I'll try to post something within the next couple of days.

Cheers