From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from [140.186.70.92] (port=59877 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1P7jDB-0002LD-Pd for qemu-devel@nongnu.org; Mon, 18 Oct 2010 02:28:46 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1P7jDA-0006fx-Dp for qemu-devel@nongnu.org; Mon, 18 Oct 2010 02:28:45 -0400 Received: from mx1.redhat.com ([209.132.183.28]:4152) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1P7jDA-0006fo-7L for qemu-devel@nongnu.org; Mon, 18 Oct 2010 02:28:44 -0400 Date: Mon, 18 Oct 2010 08:22:24 +0200 From: "Michael S. Tsirkin" Message-ID: <20101018062224.GA19214@redhat.com> References: <67902bbeea8ed4f7b776c1ea9f0d585a2374eb37.1287371107.git.yamahata@valinux.co.jp> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <67902bbeea8ed4f7b776c1ea9f0d585a2374eb37.1287371107.git.yamahata@valinux.co.jp> Subject: [Qemu-devel] Re: [PATCH v4 05/15] pci/bridge: fix pci_bridge_reset() List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Isaku Yamahata Cc: skandasa@cisco.com, adnan@khaleel.us, etmartin@cisco.com, qemu-devel@nongnu.org, wexu2@cisco.com On Mon, Oct 18, 2010 at 12:17:46PM +0900, Isaku Yamahata wrote: > lower 4bits of base/limit register is RO, and > should not be modified on reset. > > Signed-off-by: Isaku Yamahata > --- > hw/pci_bridge.c | 15 +++++++++------ > 1 files changed, 9 insertions(+), 6 deletions(-) > > diff --git a/hw/pci_bridge.c b/hw/pci_bridge.c > index 638e3b3..7229610 100644 > --- a/hw/pci_bridge.c > +++ b/hw/pci_bridge.c > @@ -161,12 +161,15 @@ void pci_bridge_reset_reg(PCIDevice *dev) > conf[PCI_SUBORDINATE_BUS] = 0; > conf[PCI_SEC_LATENCY_TIMER] = 0; > > - conf[PCI_IO_BASE] = 0; > - conf[PCI_IO_LIMIT] = 0; > - pci_set_word(conf + PCI_MEMORY_BASE, 0); > - pci_set_word(conf + PCI_MEMORY_LIMIT, 0); > - pci_set_word(conf + PCI_PREF_MEMORY_BASE, 0); > - pci_set_word(conf + PCI_PREF_MEMORY_LIMIT, 0); > + pci_clear_bit_byte(conf + PCI_IO_BASE, PCI_IO_RANGE_MASK & 0xff); > + pci_clear_bit_byte(conf + PCI_IO_LIMIT, PCI_IO_RANGE_MASK & 0xff); No need for & 0xff and & 0xfffff here and below. also, PCI spec also says that these registers' value is undefined after reset, so no need to clear them? If there's a reason, pls put it in comment. > + pci_clear_bit_word(conf + PCI_MEMORY_BASE, PCI_MEMORY_RANGE_MASK & 0xffff); > + pci_clear_bit_word(conf + PCI_MEMORY_LIMIT, > + PCI_MEMORY_RANGE_MASK & 0xffff); > + pci_clear_bit_word(conf + PCI_PREF_MEMORY_BASE, > + PCI_PREF_RANGE_MASK & 0xffff); > + pci_clear_bit_word(conf + PCI_PREF_MEMORY_LIMIT, > + PCI_PREF_RANGE_MASK & 0xffff); > pci_set_word(conf + PCI_PREF_BASE_UPPER32, 0); > pci_set_word(conf + PCI_PREF_LIMIT_UPPER32, 0); > > -- > 1.7.1.1