[Qemu-devel] Re: [PATCH v5 00/14] pcie port switch emulators

[Qemu-devel] Re: [PATCH v5 00/14] pcie port switch emulators

[Michael S. Tsirkin]

On Tue, Oct 19, 2010 at 06:06:27PM +0900, Isaku Yamahata wrote:
> On uncorrectable error status register in pcie_aer_write_config().
> The register is RW1CS, so making it writable and test-and-clear doesn't
> work.

Sure. But isn't this what w1cmask implements?

Also - mail to adnan@khaleel.us seems to bounce. I stripped it
from the Cc list for now.

-- 
MST

[Qemu-devel] Re: [PATCH v5 00/14] pcie port switch emulators

[Michael S. Tsirkin]

On Tue, Oct 19, 2010 at 06:06:27PM +0900, Isaku Yamahata wrote:
> Here is v5 of the pcie patch series.
> I hope I addressed the blockers.
> On uncorrectable error status register in pcie_aer_write_config().
> The register is RW1CS, so making it writable and test-and-clear doesn't
> work.
> 
> new patches: 1, 2, 
> updasted patches except trivial change: 4, 7, 8
> 
> BTW, as 0.13 is released, any chance to sync pci branch with
> the upstream by requesting pull?
> 
> Patch description:
> This patch series implements pcie port switch emulators
> which is basic part for pcie/q35 support.
> This is for mst/pci tree.
> 
> change v4 -> v5:
> - introduced pci_xxx_test_and_clear/set_mask
> - eliminated xxx_notify(msi_trigger, int_level)
> - eliminated FLR bits.
>   FLR will be addressed at the next phase.
> 
> changes v3 -> v4:
> - introduced new pci config helper functions.(clear set bit)
> - various clean up and some bug fixes.
> - dropped pci_shift_xxx().
> - dropped function pointerin pcie_aer.h
> - dropped pci_exp_cap(), pcie_aer_cap().
> - file rename (pcie_{root, upstream, downsatrem} => ioh33420, x3130).
> 
> changes v2 -> v3:
> - msi: improved commant and simplified shift/ffs dance
> - pci w1c config register framework
> - split pcie.[ch] into pcie_regs.h, pcie.[ch] and pcie_aer.[ch]
> - pcie, aer: many changes by following reviews.
> 
> changes v1 -> v2:
> - update msi
> - dropped already pushed out patches.
> - added msix patches.
> 
> Isaku Yamahata (14):
>   pci: introduce helper functions to test-and-{clear, set} mask in
>     configuration space
>   pci: introduce helper function to handle msi-x and msi.
>   pci: use pci_word_test_and_clear_mask() in pci_device_reset()
>   pci/bridge: fix pci_bridge_reset()
>   msi: implements msi
>   pcie: add pcie constants to pcie_regs.h
>   pcie: helper functions for pcie capability and extended capability

I'll apply these.

>   pcie/aer: helper functions for pcie aer capability

Maybe move this to the end of the series?

>   pcie port: define struct PCIEPort/PCIESlot and helper functions
>   ioh3420: pcie root port in X58 ioh
>   x3130: pcie upstream port
>   x3130: pcie downstream port
>   pcie/hotplug: introduce pushing attention button command

I think the above can be applied - just remove the dependency
on aer for now.

>   pcie/aer: glue aer error injection into qemu monitor
> 
>  Makefile.objs           |    4 +-
>  hw/ioh3420.c            |  229 +++++++++++++
>  hw/ioh3420.h            |   10 +
>  hw/msi.c                |  352 +++++++++++++++++++
>  hw/msi.h                |   41 +++
>  hw/pci.c                |   24 ++-
>  hw/pci.h                |   88 +++++-
>  hw/pci_bridge.c         |   57 +++-
>  hw/pci_bridge.h         |    2 +
>  hw/pcie.c               |  540 +++++++++++++++++++++++++++++
>  hw/pcie.h               |  113 ++++++
>  hw/pcie_aer.c           |  869 +++++++++++++++++++++++++++++++++++++++++++++++
>  hw/pcie_aer.h           |  105 ++++++
>  hw/pcie_port.c          |  198 +++++++++++
>  hw/pcie_port.h          |   51 +++
>  hw/pcie_regs.h          |  154 +++++++++
>  hw/xio3130_downstream.c |  197 +++++++++++
>  hw/xio3130_downstream.h |   11 +
>  hw/xio3130_upstream.c   |  181 ++++++++++
>  hw/xio3130_upstream.h   |   10 +
>  qemu-common.h           |    6 +
>  qemu-monitor.hx         |   36 ++
>  sysemu.h                |    9 +
>  23 files changed, 3272 insertions(+), 15 deletions(-)
>  create mode 100644 hw/ioh3420.c
>  create mode 100644 hw/ioh3420.h
>  create mode 100644 hw/msi.c
>  create mode 100644 hw/msi.h
>  create mode 100644 hw/pcie.c
>  create mode 100644 hw/pcie.h
>  create mode 100644 hw/pcie_aer.c
>  create mode 100644 hw/pcie_aer.h
>  create mode 100644 hw/pcie_port.c
>  create mode 100644 hw/pcie_port.h
>  create mode 100644 hw/pcie_regs.h
>  create mode 100644 hw/xio3130_downstream.c
>  create mode 100644 hw/xio3130_downstream.h
>  create mode 100644 hw/xio3130_upstream.c
>  create mode 100644 hw/xio3130_upstream.h

[Qemu-devel] Re: [PATCH v5 00/14] pcie port switch emulators

[Michael S. Tsirkin]

On Tue, Oct 19, 2010 at 06:06:27PM +0900, Isaku Yamahata wrote:
> Here is v5 of the pcie patch series.
> I hope I addressed the blockers.
> On uncorrectable error status register in pcie_aer_write_config().
> The register is RW1CS, so making it writable and test-and-clear doesn't
> work.
> 
> new patches: 1, 2, 
> updasted patches except trivial change: 4, 7, 8

Ok, I applied patches 1,2,3 and 5.

> BTW, as 0.13 is released, any chance to sync pci branch with
> the upstream by requesting pull?
> 
> Patch description:
> This patch series implements pcie port switch emulators
> which is basic part for pcie/q35 support.
> This is for mst/pci tree.
> 
> change v4 -> v5:
> - introduced pci_xxx_test_and_clear/set_mask
> - eliminated xxx_notify(msi_trigger, int_level)
> - eliminated FLR bits.
>   FLR will be addressed at the next phase.
> 
> changes v3 -> v4:
> - introduced new pci config helper functions.(clear set bit)
> - various clean up and some bug fixes.
> - dropped pci_shift_xxx().
> - dropped function pointerin pcie_aer.h
> - dropped pci_exp_cap(), pcie_aer_cap().
> - file rename (pcie_{root, upstream, downsatrem} => ioh33420, x3130).
> 
> changes v2 -> v3:
> - msi: improved commant and simplified shift/ffs dance
> - pci w1c config register framework
> - split pcie.[ch] into pcie_regs.h, pcie.[ch] and pcie_aer.[ch]
> - pcie, aer: many changes by following reviews.
> 
> changes v1 -> v2:
> - update msi
> - dropped already pushed out patches.
> - added msix patches.
> 
> Isaku Yamahata (14):
>   pci: introduce helper functions to test-and-{clear, set} mask in
>     configuration space
>   pci: introduce helper function to handle msi-x and msi.
>   pci: use pci_word_test_and_clear_mask() in pci_device_reset()
>   pci/bridge: fix pci_bridge_reset()
>   msi: implements msi
>   pcie: add pcie constants to pcie_regs.h
>   pcie: helper functions for pcie capability and extended capability
>   pcie/aer: helper functions for pcie aer capability
>   pcie port: define struct PCIEPort/PCIESlot and helper functions
>   ioh3420: pcie root port in X58 ioh
>   x3130: pcie upstream port
>   x3130: pcie downstream port
>   pcie/hotplug: introduce pushing attention button command
>   pcie/aer: glue aer error injection into qemu monitor
> 
>  Makefile.objs           |    4 +-
>  hw/ioh3420.c            |  229 +++++++++++++
>  hw/ioh3420.h            |   10 +
>  hw/msi.c                |  352 +++++++++++++++++++
>  hw/msi.h                |   41 +++
>  hw/pci.c                |   24 ++-
>  hw/pci.h                |   88 +++++-
>  hw/pci_bridge.c         |   57 +++-
>  hw/pci_bridge.h         |    2 +
>  hw/pcie.c               |  540 +++++++++++++++++++++++++++++
>  hw/pcie.h               |  113 ++++++
>  hw/pcie_aer.c           |  869 +++++++++++++++++++++++++++++++++++++++++++++++
>  hw/pcie_aer.h           |  105 ++++++
>  hw/pcie_port.c          |  198 +++++++++++
>  hw/pcie_port.h          |   51 +++
>  hw/pcie_regs.h          |  154 +++++++++
>  hw/xio3130_downstream.c |  197 +++++++++++
>  hw/xio3130_downstream.h |   11 +
>  hw/xio3130_upstream.c   |  181 ++++++++++
>  hw/xio3130_upstream.h   |   10 +
>  qemu-common.h           |    6 +
>  qemu-monitor.hx         |   36 ++
>  sysemu.h                |    9 +
>  23 files changed, 3272 insertions(+), 15 deletions(-)
>  create mode 100644 hw/ioh3420.c
>  create mode 100644 hw/ioh3420.h
>  create mode 100644 hw/msi.c
>  create mode 100644 hw/msi.h
>  create mode 100644 hw/pcie.c
>  create mode 100644 hw/pcie.h
>  create mode 100644 hw/pcie_aer.c
>  create mode 100644 hw/pcie_aer.h
>  create mode 100644 hw/pcie_port.c
>  create mode 100644 hw/pcie_port.h
>  create mode 100644 hw/pcie_regs.h
>  create mode 100644 hw/xio3130_downstream.c
>  create mode 100644 hw/xio3130_downstream.h
>  create mode 100644 hw/xio3130_upstream.c
>  create mode 100644 hw/xio3130_upstream.h

[Qemu-devel] Re: [PATCH v5 00/14] pcie port switch emulators

[Isaku Yamahata]

> > Isaku Yamahata (14):
> >   pci: introduce helper functions to test-and-{clear, set} mask in
> >     configuration space
> >   pci: introduce helper function to handle msi-x and msi.
> >   pci: use pci_word_test_and_clear_mask() in pci_device_reset()
> >   pci/bridge: fix pci_bridge_reset()
> >   msi: implements msi
> >   pcie: add pcie constants to pcie_regs.h
> >   pcie: helper functions for pcie capability and extended capability
> 
> I'll apply these.
> 
> >   pcie/aer: helper functions for pcie aer capability
> 
> Maybe move this to the end of the series?
> 
> >   pcie port: define struct PCIEPort/PCIESlot and helper functions
> >   ioh3420: pcie root port in X58 ioh
> >   x3130: pcie upstream port
> >   x3130: pcie downstream port
> >   pcie/hotplug: introduce pushing attention button command
> 
> I think the above can be applied - just remove the dependency
> on aer for now.

Okay. I'll update the patch series and send it tomorrow.

-- 
yamahata

[Qemu-devel] Re: [PATCH v5 00/14] pcie port switch emulators

[Isaku Yamahata]

On Tue, Oct 19, 2010 at 01:51:31PM +0200, Michael S. Tsirkin wrote:
> On Tue, Oct 19, 2010 at 06:06:27PM +0900, Isaku Yamahata wrote:
> > On uncorrectable error status register in pcie_aer_write_config().
> > The register is RW1CS, so making it writable and test-and-clear doesn't
> > work.
> 
> Sure. But isn't this what w1cmask implements?

It's not simple W1C.
Anyway I found the way to code it without the shift operation.
I'll rewrite the function with the next patch series.
-- 
yamahata

[Qemu-devel] Re: [PATCH v5 00/14] pcie port switch emulators

[Adnan Khaleel]

[-- Attachment #1: Type: text/plain, Size: 1462 bytes --]

Are all these patches going to be integrated into the current qemu repository?

-AK
  _____  

From: Isaku Yamahata [mailto:yamahata@valinux.co.jp]
To: Michael S. Tsirkin [mailto:mst@redhat.com]
Cc: qemu-devel@nongnu.org, skandasa@cisco.com, etmartin@cisco.com, wexu2@cisco.com, adnan@khaleel.us
Sent: Tue, 19 Oct 2010 08:55:29 -0500
Subject: Re: [PATCH v5 00/14] pcie port switch emulators

> > Isaku Yamahata (14):
  > >   pci: introduce helper functions to test-and-{clear, set} mask in
  > >     configuration space
  > >   pci: introduce helper function to handle msi-x and msi.
  > >   pci: use pci_word_test_and_clear_mask() in pci_device_reset()
  > >   pci/bridge: fix pci_bridge_reset()
  > >   msi: implements msi
  > >   pcie: add pcie constants to pcie_regs.h
  > >   pcie: helper functions for pcie capability and extended capability
  > 
  > I'll apply these.
  > 
  > >   pcie/aer: helper functions for pcie aer capability
  > 
  > Maybe move this to the end of the series?
  > 
  > >   pcie port: define struct PCIEPort/PCIESlot and helper functions
  > >   ioh3420: pcie root port in X58 ioh
  > >   x3130: pcie upstream port
  > >   x3130: pcie downstream port
  > >   pcie/hotplug: introduce pushing attention button command
  > 
  > I think the above can be applied - just remove the dependency
  > on aer for now.
  
  Okay. I'll update the patch series and send it tomorrow.
  
  -- 
  yamahata
    

[-- Attachment #2: Type: text/html, Size: 2109 bytes --]

[Qemu-devel] Re: [PATCH v5 00/14] pcie port switch emulators

[Michael S. Tsirkin]

On Wed, Oct 20, 2010 at 12:19:47AM +0900, Isaku Yamahata wrote:
> On Tue, Oct 19, 2010 at 01:51:31PM +0200, Michael S. Tsirkin wrote:
> > On Tue, Oct 19, 2010 at 06:06:27PM +0900, Isaku Yamahata wrote:
> > > On uncorrectable error status register in pcie_aer_write_config().
> > > The register is RW1CS, so making it writable and test-and-clear doesn't
> > > work.
> > 
> > Sure. But isn't this what w1cmask implements?
> 
> It's not simple W1C.

Well it's also sticky, but this only affects reset.
What else is different?

> Anyway I found the way to code it without the shift operation.
> I'll rewrite the function with the next patch series.
> -- 
> yamahata

[Qemu-devel] Re: [PATCH v5 00/14] pcie port switch emulators

[Isaku Yamahata]

On Tue, Oct 19, 2010 at 07:06:55PM +0200, Michael S. Tsirkin wrote:
> On Wed, Oct 20, 2010 at 12:19:47AM +0900, Isaku Yamahata wrote:
> > On Tue, Oct 19, 2010 at 01:51:31PM +0200, Michael S. Tsirkin wrote:
> > > On Tue, Oct 19, 2010 at 06:06:27PM +0900, Isaku Yamahata wrote:
> > > > On uncorrectable error status register in pcie_aer_write_config().
> > > > The register is RW1CS, so making it writable and test-and-clear doesn't
> > > > work.
> > > 
> > > Sure. But isn't this what w1cmask implements?
> > 
> > It's not simple W1C.
> 
> Well it's also sticky, but this only affects reset.
> What else is different?

The bit of uncorsta that corresponds to the first error:
        If 1b is written, the side effects takes place.
        If multiple header recording is disabled, the bit is W1C.
        If multiple header recording is enabled, the bit may or may
        not be cleared depending on whether recorded errors.
        The next error header is pulled out from the internal log.
        (the first error bit moves to the one that corresponds to
         the pulled-out one.)

The other bits of uncorsta
        If multiple header recording is disabled, the bit is W1C.
        If multiple header recording is enabled, the value isn't cleared
        even when 1b is written. So since we set w1cmask, we need to
        restore the old value.
-- 
yamahata

[Qemu-devel] Re: [PATCH v5 00/14] pcie port switch emulators

[Isaku Yamahata]

On Tue, Oct 19, 2010 at 11:07:34AM -0500, Adnan Khaleel wrote:
> Are all these patches going to be integrated into the current qemu repository?

Eventually. Right now some of them are merged into Michael's pci branch.
It's up to Michael when he requests Anthony to pull the branch.

thanks,

> 
> -AK
> 
>     ━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━
>     From: Isaku Yamahata [mailto:yamahata@valinux.co.jp]
>     To: Michael S. Tsirkin [mailto:mst@redhat.com]
>     Cc: qemu-devel@nongnu.org, skandasa@cisco.com, etmartin@cisco.com,
>     wexu2@cisco.com, adnan@khaleel.us
>     Sent: Tue, 19 Oct 2010 08:55:29 -0500
>     Subject: Re: [PATCH v5 00/14] pcie port switch emulators
> 
>     > > Isaku Yamahata (14):
>     > > pci: introduce helper functions to test-and-{clear, set} mask in
>     > > configuration space
>     > > pci: introduce helper function to handle msi-x and msi.
>     > > pci: use pci_word_test_and_clear_mask() in pci_device_reset()
>     > > pci/bridge: fix pci_bridge_reset()
>     > > msi: implements msi
>     > > pcie: add pcie constants to pcie_regs.h
>     > > pcie: helper functions for pcie capability and extended capability
>     >
>     > I'll apply these.
>     >
>     > > pcie/aer: helper functions for pcie aer capability
>     >
>     > Maybe move this to the end of the series?
>     >
>     > > pcie port: define struct PCIEPort/PCIESlot and helper functions
>     > > ioh3420: pcie root port in X58 ioh
>     > > x3130: pcie upstream port
>     > > x3130: pcie downstream port
>     > > pcie/hotplug: introduce pushing attention button command
>     >
>     > I think the above can be applied - just remove the dependency
>     > on aer for now.
> 
>     Okay. I'll update the patch series and send it tomorrow.
> 
>     --
>     yamahata
> 

-- 
yamahata

[Qemu-devel] Re: [PATCH v5 00/14] pcie port switch emulators

[Michael S. Tsirkin]

On Wed, Oct 20, 2010 at 07:36:37AM +0900, Isaku Yamahata wrote:
> On Tue, Oct 19, 2010 at 07:06:55PM +0200, Michael S. Tsirkin wrote:
> > On Wed, Oct 20, 2010 at 12:19:47AM +0900, Isaku Yamahata wrote:
> > > On Tue, Oct 19, 2010 at 01:51:31PM +0200, Michael S. Tsirkin wrote:
> > > > On Tue, Oct 19, 2010 at 06:06:27PM +0900, Isaku Yamahata wrote:
> > > > > On uncorrectable error status register in pcie_aer_write_config().
> > > > > The register is RW1CS, so making it writable and test-and-clear doesn't
> > > > > work.
> > > > 
> > > > Sure. But isn't this what w1cmask implements?
> > > 
> > > It's not simple W1C.
> > 
> > Well it's also sticky, but this only affects reset.
> > What else is different?
> 
> The bit of uncorsta that corresponds to the first error:
>         If 1b is written, the side effects takes place.
>         If multiple header recording is disabled, the bit is W1C.
>         If multiple header recording is enabled, the bit may or may
>         not be cleared depending on whether recorded errors.
>         The next error header is pulled out from the internal log.
>         (the first error bit moves to the one that corresponds to
>          the pulled-out one.)
> 
> The other bits of uncorsta
>         If multiple header recording is disabled, the bit is W1C.
>         If multiple header recording is enabled, the value isn't cleared
>         even when 1b is written. So since we set w1cmask, we need to
>         restore the old value.

I think I suggested once a good way to implement this:

- always make the bits w1c
- after config write:
  if MHR is enabled, and you see that error log is not empty and that bit is 0,
  this means that someone has written 1b.
  so pop the first error from the log, and set bit to 1 if it's not empty.

This way we only touch w1c mask on setup, no tricky range checks.
Anything wrong with this approach?

-- 
MST

[Qemu-devel] Re: [PATCH v5 00/14] pcie port switch emulators

[Isaku Yamahata]

On Wed, Oct 20, 2010 at 12:40:49AM +0200, Michael S. Tsirkin wrote:

> I think I suggested once a good way to implement this:
> 
> - always make the bits w1c
> - after config write:
>   if MHR is enabled, and you see that error log is not empty and that bit is 0,
>   this means that someone has written 1b.
>   so pop the first error from the log, and set bit to 1 if it's not empty.
> 
> This way we only touch w1c mask on setup, no tricky range checks.
> Anything wrong with this approach?

Basically okay. 
Without the range checks, we need to restore the old value to the register
if 1b isn't written to the bit of the first error.
Probably you prefer restoring it mostly always than the range check.
-- 
yamahata

[Qemu-devel] Re: [PATCH v5 00/14] pcie port switch emulators

[Michael S. Tsirkin]

On Wed, Oct 20, 2010 at 07:55:56AM +0900, Isaku Yamahata wrote:
> On Wed, Oct 20, 2010 at 12:40:49AM +0200, Michael S. Tsirkin wrote:
> 
> > I think I suggested once a good way to implement this:
> > 
> > - always make the bits w1c
> > - after config write:
> >   if MHR is enabled, and you see that error log is not empty and that bit is 0,
> >   this means that someone has written 1b.
> >   so pop the first error from the log, and set bit to 1 if it's not empty.
> > 
> > This way we only touch w1c mask on setup, no tricky range checks.
> > Anything wrong with this approach?
> 
> Basically okay. 
> Without the range checks, we need to restore the old value to the register
> if 1b isn't written to the bit of the first error.
> Probably you prefer restoring it mostly always than the range check.

Well that would be consistent with how we handle config cycles
in the rest of the code. We had a lot of tricky range checking code
and we killed it all in favor of making operations idempotent so
they are safe to redo on each config cycle.

-- 
MST

[Qemu-devel] Re: [PATCH v5 00/14] pcie port switch emulators

[Wei Xu]

Isaku,

Good work! One question here: any plan to put q35 and seabios into mainline?

FYI: I have made pcie plus q35 working on qemu-kvm, though on a little bit
old code base.

Wei


On 10/19/10 3:39 PM, "Isaku Yamahata" <yamahata@valinux.co.jp> wrote:

> On Tue, Oct 19, 2010 at 11:07:34AM -0500, Adnan Khaleel wrote:
>> Are all these patches going to be integrated into the current qemu
>> repository?
> 
> Eventually. Right now some of them are merged into Michael's pci branch.
> It's up to Michael when he requests Anthony to pull the branch.
> 
> thanks,
> 
>> 
>> -AK
>> 
>>     ━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━
>>     From: Isaku Yamahata [mailto:yamahata@valinux.co.jp]
>>     To: Michael S. Tsirkin [mailto:mst@redhat.com]
>>     Cc: qemu-devel@nongnu.org, skandasa@cisco.com, etmartin@cisco.com,
>>     wexu2@cisco.com, adnan@khaleel.us
>>     Sent: Tue, 19 Oct 2010 08:55:29 -0500
>>     Subject: Re: [PATCH v5 00/14] pcie port switch emulators
>> 
>>>> Isaku Yamahata (14):
>>>> pci: introduce helper functions to test-and-{clear, set} mask in
>>>> configuration space
>>>> pci: introduce helper function to handle msi-x and msi.
>>>> pci: use pci_word_test_and_clear_mask() in pci_device_reset()
>>>> pci/bridge: fix pci_bridge_reset()
>>>> msi: implements msi
>>>> pcie: add pcie constants to pcie_regs.h
>>>> pcie: helper functions for pcie capability and extended capability
>>> 
>>> I'll apply these.
>>> 
>>>> pcie/aer: helper functions for pcie aer capability
>>> 
>>> Maybe move this to the end of the series?
>>> 
>>>> pcie port: define struct PCIEPort/PCIESlot and helper functions
>>>> ioh3420: pcie root port in X58 ioh
>>>> x3130: pcie upstream port
>>>> x3130: pcie downstream port
>>>> pcie/hotplug: introduce pushing attention button command
>>> 
>>> I think the above can be applied - just remove the dependency
>>> on aer for now.
>> 
>>     Okay. I'll update the patch series and send it tomorrow.
>> 
>>     --
>>     yamahata
>> 

[Qemu-devel] Re: [PATCH v5 00/14] pcie port switch emulators

[Michael S. Tsirkin]

On Wed, Oct 20, 2010 at 08:17:24AM +0900, Isaku Yamahata wrote:
> On Tue, Oct 19, 2010 at 04:05:28PM -0700, Wei Xu wrote:
> > Good work! One question here: any plan to put q35 and seabios into mainline?
> 
> My plan is
> qemu part:
> 1. respin this patch. Mainly aer part. <<< I'm here 
> 2. address bus reset and flr.
> 3. Then move on to q35 north/south bridge.
> 
> After 1 or 2, it would be desirable to rebase my local working q35 repo.
> So I'd like Michael to request Anthony to pull the pci branch into
> the upstream once the aer patches are merged.

Yes, this makes sense. We don't need to wait for flr I think.

-- 
MST

[Qemu-devel] Re: [PATCH v5 00/14] pcie port switch emulators

[Isaku Yamahata]

On Tue, Oct 19, 2010 at 04:05:28PM -0700, Wei Xu wrote:
> Good work! One question here: any plan to put q35 and seabios into mainline?

My plan is
qemu part:
1. respin this patch. Mainly aer part. <<< I'm here 
2. address bus reset and flr.
3. Then move on to q35 north/south bridge.

After 1 or 2, it would be desirable to rebase my local working q35 repo.
So I'd like Michael to request Anthony to pull the pci branch into
the upstream once the aer patches are merged.

seabios part:
- two acpi related patches are pending.
- dev-q35.c
- acpi DSDT tables for q35


> FYI: I have made pcie plus q35 working on qemu-kvm, though on a little bit
> old code base.

Great news. I'd like to have a look at the code.

thanks,

> 
> Wei
> 
> 
> On 10/19/10 3:39 PM, "Isaku Yamahata" <yamahata@valinux.co.jp> wrote:
> 
> > On Tue, Oct 19, 2010 at 11:07:34AM -0500, Adnan Khaleel wrote:
> >> Are all these patches going to be integrated into the current qemu
> >> repository?
> > 
> > Eventually. Right now some of them are merged into Michael's pci branch.
> > It's up to Michael when he requests Anthony to pull the branch.
> > 
> > thanks,
> > 
> >> 
> >> -AK
> >> 
> >>     ━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━
> >>     From: Isaku Yamahata [mailto:yamahata@valinux.co.jp]
> >>     To: Michael S. Tsirkin [mailto:mst@redhat.com]
> >>     Cc: qemu-devel@nongnu.org, skandasa@cisco.com, etmartin@cisco.com,
> >>     wexu2@cisco.com, adnan@khaleel.us
> >>     Sent: Tue, 19 Oct 2010 08:55:29 -0500
> >>     Subject: Re: [PATCH v5 00/14] pcie port switch emulators
> >> 
> >>>> Isaku Yamahata (14):
> >>>> pci: introduce helper functions to test-and-{clear, set} mask in
> >>>> configuration space
> >>>> pci: introduce helper function to handle msi-x and msi.
> >>>> pci: use pci_word_test_and_clear_mask() in pci_device_reset()
> >>>> pci/bridge: fix pci_bridge_reset()
> >>>> msi: implements msi
> >>>> pcie: add pcie constants to pcie_regs.h
> >>>> pcie: helper functions for pcie capability and extended capability
> >>> 
> >>> I'll apply these.
> >>> 
> >>>> pcie/aer: helper functions for pcie aer capability
> >>> 
> >>> Maybe move this to the end of the series?
> >>> 
> >>>> pcie port: define struct PCIEPort/PCIESlot and helper functions
> >>>> ioh3420: pcie root port in X58 ioh
> >>>> x3130: pcie upstream port
> >>>> x3130: pcie downstream port
> >>>> pcie/hotplug: introduce pushing attention button command
> >>> 
> >>> I think the above can be applied - just remove the dependency
> >>> on aer for now.
> >> 
> >>     Okay. I'll update the patch series and send it tomorrow.
> >> 
> >>     --
> >>     yamahata
> >> 
> 

-- 
yamahata

[Qemu-devel] Re: [PATCH v5 00/14] pcie port switch emulators

[Wei Xu]

Isaku,

Sure I will send out patch after some cleanup. MSI using irq-in-kernel still
a little bit ugly:)

Wei


On 10/19/10 4:17 PM, "Isaku Yamahata" <yamahata@valinux.co.jp> wrote:

> On Tue, Oct 19, 2010 at 04:05:28PM -0700, Wei Xu wrote:
>> Good work! One question here: any plan to put q35 and seabios into mainline?
> 
> My plan is
> qemu part:
> 1. respin this patch. Mainly aer part. <<< I'm here
> 2. address bus reset and flr.
> 3. Then move on to q35 north/south bridge.
> 
> After 1 or 2, it would be desirable to rebase my local working q35 repo.
> So I'd like Michael to request Anthony to pull the pci branch into
> the upstream once the aer patches are merged.
> 
> seabios part:
> - two acpi related patches are pending.
> - dev-q35.c
> - acpi DSDT tables for q35
> 
> 
>> FYI: I have made pcie plus q35 working on qemu-kvm, though on a little bit
>> old code base.
> 
> Great news. I'd like to have a look at the code.
> 
> thanks,
> 
>> 
>> Wei
>> 
>> 
>> On 10/19/10 3:39 PM, "Isaku Yamahata" <yamahata@valinux.co.jp> wrote:
>> 
>>> On Tue, Oct 19, 2010 at 11:07:34AM -0500, Adnan Khaleel wrote:
>>>> Are all these patches going to be integrated into the current qemu
>>>> repository?
>>> 
>>> Eventually. Right now some of them are merged into Michael's pci branch.
>>> It's up to Michael when he requests Anthony to pull the branch.
>>> 
>>> thanks,
>>> 
>>>> 
>>>> -AK
>>>> 
>>>>     ━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━━
>>>>     From: Isaku Yamahata [mailto:yamahata@valinux.co.jp]
>>>>     To: Michael S. Tsirkin [mailto:mst@redhat.com]
>>>>     Cc: qemu-devel@nongnu.org, skandasa@cisco.com, etmartin@cisco.com,
>>>>     wexu2@cisco.com, adnan@khaleel.us
>>>>     Sent: Tue, 19 Oct 2010 08:55:29 -0500
>>>>     Subject: Re: [PATCH v5 00/14] pcie port switch emulators
>>>> 
>>>>>> Isaku Yamahata (14):
>>>>>> pci: introduce helper functions to test-and-{clear, set} mask in
>>>>>> configuration space
>>>>>> pci: introduce helper function to handle msi-x and msi.
>>>>>> pci: use pci_word_test_and_clear_mask() in pci_device_reset()
>>>>>> pci/bridge: fix pci_bridge_reset()
>>>>>> msi: implements msi
>>>>>> pcie: add pcie constants to pcie_regs.h
>>>>>> pcie: helper functions for pcie capability and extended capability
>>>>> 
>>>>> I'll apply these.
>>>>> 
>>>>>> pcie/aer: helper functions for pcie aer capability
>>>>> 
>>>>> Maybe move this to the end of the series?
>>>>> 
>>>>>> pcie port: define struct PCIEPort/PCIESlot and helper functions
>>>>>> ioh3420: pcie root port in X58 ioh
>>>>>> x3130: pcie upstream port
>>>>>> x3130: pcie downstream port
>>>>>> pcie/hotplug: introduce pushing attention button command
>>>>> 
>>>>> I think the above can be applied - just remove the dependency
>>>>> on aer for now.
>>>> 
>>>>     Okay. I'll update the patch series and send it tomorrow.
>>>> 
>>>>     --
>>>>     yamahata
>>>> 
>>