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Date: Wed, 20 Oct 2010 07:36:37 +0900
From: Isaku Yamahata <yamahata@valinux.co.jp>
Message-ID: <20101019223637.GC30021@valinux.co.jp>
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Subject: [Qemu-devel] Re: [PATCH v5 00/14] pcie port switch emulators
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To: "Michael S. Tsirkin" <mst@redhat.com>
Cc: skandasa@cisco.com, etmartin@cisco.com, qemu-devel@nongnu.org, wexu2@cisco.com

On Tue, Oct 19, 2010 at 07:06:55PM +0200, Michael S. Tsirkin wrote:
> On Wed, Oct 20, 2010 at 12:19:47AM +0900, Isaku Yamahata wrote:
> > On Tue, Oct 19, 2010 at 01:51:31PM +0200, Michael S. Tsirkin wrote:
> > > On Tue, Oct 19, 2010 at 06:06:27PM +0900, Isaku Yamahata wrote:
> > > > On uncorrectable error status register in pcie_aer_write_config().
> > > > The register is RW1CS, so making it writable and test-and-clear doesn't
> > > > work.
> > > 
> > > Sure. But isn't this what w1cmask implements?
> > 
> > It's not simple W1C.
> 
> Well it's also sticky, but this only affects reset.
> What else is different?

The bit of uncorsta that corresponds to the first error:
        If 1b is written, the side effects takes place.
        If multiple header recording is disabled, the bit is W1C.
        If multiple header recording is enabled, the bit may or may
        not be cleared depending on whether recorded errors.
        The next error header is pulled out from the internal log.
        (the first error bit moves to the one that corresponds to
         the pulled-out one.)

The other bits of uncorsta
        If multiple header recording is disabled, the bit is W1C.
        If multiple header recording is enabled, the value isn't cleared
        even when 1b is written. So since we set w1cmask, we need to
        restore the old value.
-- 
yamahata