From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from [140.186.70.92] (port=45440 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1PB6kZ-0002z0-9Q for qemu-devel@nongnu.org; Wed, 27 Oct 2010 10:13:12 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1PB6kY-0006MC-0O for qemu-devel@nongnu.org; Wed, 27 Oct 2010 10:13:11 -0400 Received: from mx1.redhat.com ([209.132.183.28]:43239) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1PB6kX-0006Ls-QU for qemu-devel@nongnu.org; Wed, 27 Oct 2010 10:13:09 -0400 Date: Wed, 27 Oct 2010 18:12:28 +0200 From: "Michael S. Tsirkin" Message-ID: <20101027161227.GA9873@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Subject: [Qemu-devel] bonito: PCI_STATUS questions List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org, zltjiangshi@gmail.com, Aurelien Jarno I see code in bonito.c that clears bits: PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_REC_TARGET_ABORT on each read and write. However 1. I don't see anything in code that would set these bits 2. The PCI spec says this about the status register: Reads to this register behave normally. Writes are slightly different in that bits can be reset, but not set. A one bit is reset (if it is not read-only) whenever the register is written, and the write data in the corresponding bit location is a 1. For instance, to clear bit 14 and not affect any other bits, write the value 0100_0000_0000_0000b to the register. while the code in bonito.c resets the bits to 0 on each write. Comments? -- MST