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Date: Thu, 28 Oct 2010 06:54:26 +0200
From: "Michael S. Tsirkin" <mst@redhat.com>
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Subject: [Qemu-devel] Re: bonito: PCI_STATUS questions
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To: chen huacai <zltjiangshi@gmail.com>
Cc: qemu-devel@nongnu.org, Aurelien Jarno <aurelien@aurel32.net>

On Thu, Oct 28, 2010 at 08:57:01AM +0800, chen huacai wrote:
> Because the code in PMON and Linux kernel use these bits to verify r/w
> operations. If one of them is 1 after r/w, PMON and Linux will
> consider r/w has failed.

Where's that code in Linux?

> I guess that software will not set them to 1, because it is set by
> hardware when operation fails.

So I guess just making these write 1 to clear according to spec will work=
?

> On Thu, Oct 28, 2010 at 12:12 AM, Michael S. Tsirkin <mst@redhat.com> w=
rote:
> > I see code in bonito.c that clears bits:
> > PCI_STATUS_REC_MASTER_ABORT | PCI_STATUS_REC_TARGET_ABORT
> > on each read and write.
> >
> > However
> > 1. I don't see anything in code that would set these bits
> > 2. The PCI spec says this about the status register:
> >
> > =A0 =A0 =A0 =A0Reads to this register behave normally. Writes are sli=
ghtly different in
> > =A0 =A0 =A0 =A0that bits can be reset, but not set. A one bit is rese=
t (if it is not
> > =A0 =A0 =A0 =A0read-only) whenever the register is written, and the w=
rite data in the
> > =A0 =A0 =A0 =A0corresponding bit location is a 1. For instance, to cl=
ear bit 14 and not
> > =A0 =A0 =A0 =A0affect any other bits, write the value 0100_0000_0000_=
0000b to the
> > =A0 =A0 =A0 =A0register.
> >
> > while the code in bonito.c resets the bits to 0 on each write.
> >
> > Comments?
> >
> > --
> > MST
> >
>=20
>=20
>=20
> --=20
> Huacai Chen