* [Qemu-devel] [PATCH v8 00/11] pcie port switch emulators
@ 2010-11-15 7:30 Isaku Yamahata
2010-11-15 7:30 ` [Qemu-devel] [PATCH v8 01/11] pci: revise pci command register initialization Isaku Yamahata
` (10 more replies)
0 siblings, 11 replies; 16+ messages in thread
From: Isaku Yamahata @ 2010-11-15 7:30 UTC (permalink / raw)
To: qemu-devel; +Cc: skandasa, adnan, wexu2, mst, yamahata, etmartin
Here is v8 of the pcie switch emulators patch.
This is for qemu main tree.
Patch description:
The patch series adds pcie/aer functionality to the pcie port emulators
and adds new qemu command to inject aer into the guest.
Changes v7 -> v8:
- Added command to the forward declaration.
- revise pci command/status register initialization
- various changes to follow the review
- use domain:slot.func:slot.func..:slot.func to specify pci function
instead of domain:bus:slot.func
- allow symbolic name for aer error name in addition to 32 bit value
Changes v6 -> v7:
- the glue patch for pushing attention button is dropped for now.
This will be addressed later.
- various clean up of aer helper functions.
changes v5 -> v6:
- dropped already merged patches.
- add comment on hpev_intx
- updated the bridge fix patch
- update the aer patch.
- reordered the patch series to remove the aer dependency.
change v4 -> v5:
- introduced pci_xxx_test_and_clear/set_mask
- eliminated xxx_notify(msi_trigger, int_level)
- eliminated FLR bits.
FLR will be addressed at the next phase.
changes v3 -> v4:
- introduced new pci config helper functions.(clear set bit)
- various clean up and some bug fixes.
- dropped pci_shift_xxx().
- dropped function pointerin pcie_aer.h
- dropped pci_exp_cap(), pcie_aer_cap().
- file rename (pcie_{root, upstream, downsatrem} => ioh33420, x3130).
changes v2 -> v3:
- msi: improved commant and simplified shift/ffs dance
- pci w1c config register framework
- split pcie.[ch] into pcie_regs.h, pcie.[ch] and pcie_aer.[ch]
- pcie, aer: many changes by following reviews.
changes v1 -> v2:
- update msi
- dropped already pushed out patches.
- added msix patches.
Isaku Yamahata (11):
pci: revise pci command register initialization
pci: clean up pci command register io/memory bit initialization
pci: fix accesses to pci status register
pci: clean up of pci status register
pcie_regs.h: more constants
pcie/aer: helper functions for pcie aer capability
pci: introduce a parser for pci device path
pcie/aer: glue aer error injection into qemu monitor
ioh3420: support aer
x3130/upstream: support aer
x3130/downstream: support aer.
Makefile.objs | 2 +-
hmp-commands.hx | 23 +
hw/ioh3420.c | 51 ++-
hw/pci.c | 207 +++++++++-
hw/pci.h | 1 +
hw/pcie.h | 14 +
hw/pcie_aer.c | 1045 +++++++++++++++++++++++++++++++++++++++++++++++
hw/pcie_aer.h | 106 +++++
hw/pcie_regs.h | 2 +
hw/xio3130_downstream.c | 13 +-
hw/xio3130_upstream.c | 12 +-
qemu-common.h | 3 +
sysemu.h | 5 +
13 files changed, 1456 insertions(+), 28 deletions(-)
create mode 100644 hw/pcie_aer.c
create mode 100644 hw/pcie_aer.h
^ permalink raw reply [flat|nested] 16+ messages in thread
* [Qemu-devel] [PATCH v8 01/11] pci: revise pci command register initialization
2010-11-15 7:30 [Qemu-devel] [PATCH v8 00/11] pcie port switch emulators Isaku Yamahata
@ 2010-11-15 7:30 ` Isaku Yamahata
2010-11-15 8:09 ` [Qemu-devel] " Michael S. Tsirkin
2010-11-15 7:30 ` [Qemu-devel] [PATCH v8 02/11] pci: clean up pci command register io/memory bit initialization Isaku Yamahata
` (9 subsequent siblings)
10 siblings, 1 reply; 16+ messages in thread
From: Isaku Yamahata @ 2010-11-15 7:30 UTC (permalink / raw)
To: qemu-devel; +Cc: skandasa, adnan, wexu2, mst, yamahata, etmartin
This patch cleans up command register initialization with
comments.
Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>
---
hw/pci.c | 42 ++++++++++++++++++++++++++++++++++++++++++
1 files changed, 42 insertions(+), 0 deletions(-)
diff --git a/hw/pci.c b/hw/pci.c
index 962886e..b70a568 100644
--- a/hw/pci.c
+++ b/hw/pci.c
@@ -544,8 +544,50 @@ static void pci_init_wmask(PCIDevice *dev)
dev->wmask[PCI_CACHE_LINE_SIZE] = 0xff;
dev->wmask[PCI_INTERRUPT_LINE] = 0xff;
+
+ /*
+ * bit 0: PCI_COMMAND_IO
+ * type 0: if IO BAR is used, RW
+ * type 1: RW
+ * bit 1: PCI_COMMAND_MEMORY
+ * type 0: if IO BAR is used, RW
+ * type 1: RW
+ * bit 2: PCI_COMMAND_MASTER
+ * type 0: RW if bus master
+ * type 1: RW
+ * bit 3: PCI_COMMAND_SPECIAL
+ * RO=0, optionally RW: Such device should set this bit itself
+ * bit 4: PCI_COMMAND_INVALIDATE
+ * RO=0, optionally RW: Such device should set this bit itself
+ * bit 5: PCI_COMMAND_VGA_PALETTE
+ * RO=0, optionally RW: Such device should set this bit itself
+ * bit 6: PCI_COMMAND_PARITY
+ * RW with exceptions: Such device should clear this bit itself
+ * Given that qemu doesn't emulate pci bus cycles, so that there
+ * is no place to generate parity error. So just making this
+ * register RW is okay because there is no place which refers
+ * this bit.
+ * TODO: When device assignment tried to inject PERR# into qemu,
+ * some extra work would be needed.
+ * bit 7: PCI_COMMAND_WAIT: reserved (PCI 3.0)
+ * RO=0
+ * bit 8: PCI_COMMAND_SERR
+ * RW with exceptions: Such device should clear this bit itself
+ * Given that qemu doesn't emulate pci bus cycles, so that there
+ * is no place to generate system error. So just making this
+ * register RW is okay because there is no place which refers
+ * this bit.
+ * TODO: When device assignment tried to inject SERR# into qemu,
+ * some extra work would be needed.
+ * bit 9: PCI_COMMAND_FAST_BACK
+ * RO=0, optionally RW: Such device should set this bit itself
+ * bit 10: PCI_COMMAND_INTX_DISABLE
+ * RW
+ * bit 11-15: reserved
+ */
pci_set_word(dev->wmask + PCI_COMMAND,
PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
+ PCI_COMMAND_PARITY | PCI_COMMAND_SERR |
PCI_COMMAND_INTX_DISABLE);
memset(dev->wmask + PCI_CONFIG_HEADER_SIZE, 0xff,
--
1.7.1.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [Qemu-devel] [PATCH v8 02/11] pci: clean up pci command register io/memory bit initialization
2010-11-15 7:30 [Qemu-devel] [PATCH v8 00/11] pcie port switch emulators Isaku Yamahata
2010-11-15 7:30 ` [Qemu-devel] [PATCH v8 01/11] pci: revise pci command register initialization Isaku Yamahata
@ 2010-11-15 7:30 ` Isaku Yamahata
2010-11-15 7:30 ` [Qemu-devel] [PATCH v8 03/11] pci: fix accesses to pci status register Isaku Yamahata
` (8 subsequent siblings)
10 siblings, 0 replies; 16+ messages in thread
From: Isaku Yamahata @ 2010-11-15 7:30 UTC (permalink / raw)
To: qemu-devel; +Cc: skandasa, adnan, wexu2, mst, yamahata, etmartin
This patch fixes the initialization of io/memory bit of command register.
Those bits for type 1 device is RW.
Those bits for type 0 device is
RO = 0 if it has no io/memory BAR
RW if it has io/memory BAR
Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>
---
hw/pci.c | 20 +++++++++++++++++---
1 files changed, 17 insertions(+), 3 deletions(-)
diff --git a/hw/pci.c b/hw/pci.c
index b70a568..2fc8ab1 100644
--- a/hw/pci.c
+++ b/hw/pci.c
@@ -548,10 +548,14 @@ static void pci_init_wmask(PCIDevice *dev)
/*
* bit 0: PCI_COMMAND_IO
* type 0: if IO BAR is used, RW
- * type 1: RW
+ * This is handled by pci_register_bar()
+ * type 1: RW:
+ * This is fixed by pci_init_wmask_bridge()
* bit 1: PCI_COMMAND_MEMORY
* type 0: if IO BAR is used, RW
+ * This is handled by pci_register_bar()
* type 1: RW
+ * This is fixed by pci_init_wmask_bridge()
* bit 2: PCI_COMMAND_MASTER
* type 0: RW if bus master
* type 1: RW
@@ -586,8 +590,7 @@ static void pci_init_wmask(PCIDevice *dev)
* bit 11-15: reserved
*/
pci_set_word(dev->wmask + PCI_COMMAND,
- PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
- PCI_COMMAND_PARITY | PCI_COMMAND_SERR |
+ PCI_COMMAND_MASTER | PCI_COMMAND_PARITY | PCI_COMMAND_SERR |
PCI_COMMAND_INTX_DISABLE);
memset(dev->wmask + PCI_CONFIG_HEADER_SIZE, 0xff,
@@ -596,6 +599,9 @@ static void pci_init_wmask(PCIDevice *dev)
static void pci_init_wmask_bridge(PCIDevice *d)
{
+ pci_word_test_and_set_mask(d->wmask + PCI_COMMAND,
+ PCI_COMMAND_IO | PCI_COMMAND_MEMORY);
+
/* PCI_PRIMARY_BUS, PCI_SECONDARY_BUS, PCI_SUBORDINATE_BUS and
PCI_SEC_LETENCY_TIMER */
memset(d->wmask + PCI_PRIMARY_BUS, 0xff, 4);
@@ -833,6 +839,14 @@ void pci_register_bar(PCIDevice *pci_dev, int region_num,
if (region_num == PCI_ROM_SLOT) {
/* ROM enable bit is writeable */
wmask |= PCI_ROM_ADDRESS_ENABLE;
+ } else {
+ if (r->type & PCI_BASE_ADDRESS_SPACE_IO) {
+ pci_word_test_and_set_mask(pci_dev->wmask + PCI_COMMAND,
+ PCI_COMMAND_IO);
+ } else {
+ pci_word_test_and_set_mask(pci_dev->wmask + PCI_COMMAND,
+ PCI_COMMAND_MEMORY);
+ }
}
pci_set_long(pci_dev->config + addr, type);
if (!(r->type & PCI_BASE_ADDRESS_SPACE_IO) &&
--
1.7.1.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [Qemu-devel] [PATCH v8 03/11] pci: fix accesses to pci status register
2010-11-15 7:30 [Qemu-devel] [PATCH v8 00/11] pcie port switch emulators Isaku Yamahata
2010-11-15 7:30 ` [Qemu-devel] [PATCH v8 01/11] pci: revise pci command register initialization Isaku Yamahata
2010-11-15 7:30 ` [Qemu-devel] [PATCH v8 02/11] pci: clean up pci command register io/memory bit initialization Isaku Yamahata
@ 2010-11-15 7:30 ` Isaku Yamahata
2010-11-15 7:30 ` [Qemu-devel] [PATCH v8 04/11] pci: clean up of " Isaku Yamahata
` (7 subsequent siblings)
10 siblings, 0 replies; 16+ messages in thread
From: Isaku Yamahata @ 2010-11-15 7:30 UTC (permalink / raw)
To: qemu-devel; +Cc: skandasa, adnan, wexu2, mst, yamahata, etmartin
pci status register is 16 bit, not 8 bit.
So use helper function to manipulate status register.
Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>
---
hw/pci.c | 21 +++++++++++++--------
1 files changed, 13 insertions(+), 8 deletions(-)
diff --git a/hw/pci.c b/hw/pci.c
index 2fc8ab1..52fe655 100644
--- a/hw/pci.c
+++ b/hw/pci.c
@@ -127,9 +127,11 @@ static void pci_change_irq_level(PCIDevice *pci_dev, int irq_num, int change)
static void pci_update_irq_status(PCIDevice *dev)
{
if (dev->irq_state) {
- dev->config[PCI_STATUS] |= PCI_STATUS_INTERRUPT;
+ pci_word_test_and_set_mask(dev->config + PCI_STATUS,
+ PCI_STATUS_INTERRUPT);
} else {
- dev->config[PCI_STATUS] &= ~PCI_STATUS_INTERRUPT;
+ pci_word_test_and_clear_mask(dev->config + PCI_STATUS,
+ PCI_STATUS_INTERRUPT);
}
}
@@ -404,7 +406,7 @@ void pci_device_save(PCIDevice *s, QEMUFile *f)
* in irq_state which we are saving.
* This makes us compatible with old devices
* which never set or clear this bit. */
- s->config[PCI_STATUS] &= ~PCI_STATUS_INTERRUPT;
+ pci_word_test_and_clear_mask(s->config + PCI_STATUS, PCI_STATUS_INTERRUPT);
vmstate_save_state(f, pci_get_vmstate(s), s);
/* Restore the interrupt status bit. */
pci_update_irq_status(s);
@@ -530,7 +532,7 @@ static void pci_init_cmask(PCIDevice *dev)
{
pci_set_word(dev->cmask + PCI_VENDOR_ID, 0xffff);
pci_set_word(dev->cmask + PCI_DEVICE_ID, 0xffff);
- dev->cmask[PCI_STATUS] = PCI_STATUS_CAP_LIST;
+ pci_set_word(dev->cmask + PCI_STATUS, PCI_STATUS_CAP_LIST);
dev->cmask[PCI_REVISION_ID] = 0xff;
dev->cmask[PCI_CLASS_PROG] = 0xff;
pci_set_word(dev->cmask + PCI_CLASS_DEVICE, 0xffff);
@@ -1697,8 +1699,9 @@ static uint8_t pci_find_capability_list(PCIDevice *pdev, uint8_t cap_id,
{
uint8_t next, prev;
- if (!(pdev->config[PCI_STATUS] & PCI_STATUS_CAP_LIST))
+ if (!(pci_get_word(pdev->config + PCI_STATUS) & PCI_STATUS_CAP_LIST)) {
return 0;
+ }
for (prev = PCI_CAPABILITY_LIST; (next = pdev->config[prev]);
prev = next + PCI_CAP_LIST_NEXT)
@@ -1804,7 +1807,7 @@ int pci_add_capability(PCIDevice *pdev, uint8_t cap_id,
config[PCI_CAP_LIST_ID] = cap_id;
config[PCI_CAP_LIST_NEXT] = pdev->config[PCI_CAPABILITY_LIST];
pdev->config[PCI_CAPABILITY_LIST] = offset;
- pdev->config[PCI_STATUS] |= PCI_STATUS_CAP_LIST;
+ pci_word_test_and_set_mask(pdev->config + PCI_STATUS, PCI_STATUS_CAP_LIST);
memset(pdev->used + offset, 0xFF, size);
/* Make capability read-only by default */
memset(pdev->wmask + offset, 0, size);
@@ -1827,8 +1830,10 @@ void pci_del_capability(PCIDevice *pdev, uint8_t cap_id, uint8_t size)
memset(pdev->cmask + offset, 0, size);
memset(pdev->used + offset, 0, size);
- if (!pdev->config[PCI_CAPABILITY_LIST])
- pdev->config[PCI_STATUS] &= ~PCI_STATUS_CAP_LIST;
+ if (!pdev->config[PCI_CAPABILITY_LIST]) {
+ pci_word_test_and_clear_mask(pdev->config + PCI_STATUS,
+ PCI_STATUS_CAP_LIST);
+ }
}
/* Reserve space for capability at a known offset (to call after load). */
--
1.7.1.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [Qemu-devel] [PATCH v8 04/11] pci: clean up of pci status register
2010-11-15 7:30 [Qemu-devel] [PATCH v8 00/11] pcie port switch emulators Isaku Yamahata
` (2 preceding siblings ...)
2010-11-15 7:30 ` [Qemu-devel] [PATCH v8 03/11] pci: fix accesses to pci status register Isaku Yamahata
@ 2010-11-15 7:30 ` Isaku Yamahata
2010-11-15 7:30 ` [Qemu-devel] [PATCH v8 05/11] pcie_regs.h: more constants Isaku Yamahata
` (6 subsequent siblings)
10 siblings, 0 replies; 16+ messages in thread
From: Isaku Yamahata @ 2010-11-15 7:30 UTC (permalink / raw)
To: qemu-devel; +Cc: skandasa, adnan, wexu2, mst, yamahata, etmartin
This patch refine the initialization/reset of
pci status registers.
Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>
---
hw/pci.c | 41 +++++++++++++++++++++++++++++++++++++++--
1 files changed, 39 insertions(+), 2 deletions(-)
diff --git a/hw/pci.c b/hw/pci.c
index 52fe655..fba765b 100644
--- a/hw/pci.c
+++ b/hw/pci.c
@@ -145,6 +145,9 @@ static void pci_device_reset(PCIDevice *dev)
pci_word_test_and_clear_mask(dev->config + PCI_COMMAND,
pci_get_word(dev->wmask + PCI_COMMAND) |
pci_get_word(dev->w1cmask + PCI_COMMAND));
+ pci_word_test_and_clear_mask(dev->config + PCI_STATUS,
+ pci_get_word(dev->wmask + PCI_STATUS) |
+ pci_get_word(dev->w1cmask + PCI_STATUS));
dev->config[PCI_CACHE_LINE_SIZE] = 0x0;
dev->config[PCI_INTERRUPT_LINE] = 0x0;
for (r = 0; r < PCI_NUM_REGIONS; ++r) {
@@ -540,7 +543,7 @@ static void pci_init_cmask(PCIDevice *dev)
dev->cmask[PCI_CAPABILITY_LIST] = 0xff;
}
-static void pci_init_wmask(PCIDevice *dev)
+static void pci_init_wmask_w1cmask(PCIDevice *dev)
{
int config_size = pci_config_size(dev);
@@ -595,6 +598,40 @@ static void pci_init_wmask(PCIDevice *dev)
PCI_COMMAND_MASTER | PCI_COMMAND_PARITY | PCI_COMMAND_SERR |
PCI_COMMAND_INTX_DISABLE);
+ /*
+ * bit 0-2: reserved
+ * bit 3: PCI_STATUS_INTERRUPT: RO
+ * bit 4: PCI_STATUS_CAP_LIST: RO
+ * bit 5: PCI_STATUS_66MHZ: RO
+ * bit 6: PCI_STATUS_UDF: reserved (PCI 2.2-)
+ * bit 7: PCI_STATUS_FAST_BACK: RO
+ * bit 8: PCI_STATUS_PARITY
+ * type 0: RW for bus master
+ * type 1: RW1C
+ * bit 9-10: PCI_STATUS_DEVSEL: RO
+ * bit 11: PCI_STATUS_SIG_TARGET_ABORT
+ * type 0: RW1C for targets that is capable of terminating
+ * a transaction.
+ * type 1: RW1C
+ * bit 12: PCI_STATUS_REC_TARGET_ABORT
+ * type 0: RW1C for masters
+ * type 1: RW1C
+ * bit 13: PCI_STATUS_REC_MASTER_ABORT
+ * type 0: RW1C for masters
+ * type 1: RW1C
+ * bit 14: PCI_STATUS_SIG_SYSTEM_ERROR
+ * type 0: RW1C with execptions
+ * type 1: RW1C
+ * bit : PCI_STATUS_DETECTED_PARITY: RW1C
+ *
+ * It's okay to set w1mask even for RO=0(i.e. reserved) because
+ * writing value 1 to w1c bit whose value is 0 has no effect.
+ */
+ pci_set_word(dev->w1cmask + PCI_STATUS,
+ PCI_STATUS_PARITY | PCI_STATUS_SIG_TARGET_ABORT |
+ PCI_STATUS_REC_TARGET_ABORT | PCI_STATUS_REC_MASTER_ABORT |
+ PCI_STATUS_SIG_SYSTEM_ERROR | PCI_STATUS_DETECTED_PARITY);
+
memset(dev->wmask + PCI_CONFIG_HEADER_SIZE, 0xff,
config_size - PCI_CONFIG_HEADER_SIZE);
}
@@ -725,7 +762,7 @@ static PCIDevice *do_pci_register_device(PCIDevice *pci_dev, PCIBus *bus,
pci_set_default_subsystem_id(pci_dev);
}
pci_init_cmask(pci_dev);
- pci_init_wmask(pci_dev);
+ pci_init_wmask_w1cmask(pci_dev);
if (is_bridge) {
pci_init_wmask_bridge(pci_dev);
}
--
1.7.1.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [Qemu-devel] [PATCH v8 05/11] pcie_regs.h: more constants
2010-11-15 7:30 [Qemu-devel] [PATCH v8 00/11] pcie port switch emulators Isaku Yamahata
` (3 preceding siblings ...)
2010-11-15 7:30 ` [Qemu-devel] [PATCH v8 04/11] pci: clean up of " Isaku Yamahata
@ 2010-11-15 7:30 ` Isaku Yamahata
2010-11-15 7:30 ` [Qemu-devel] [PATCH v8 06/11] pcie/aer: helper functions for pcie aer capability Isaku Yamahata
` (5 subsequent siblings)
10 siblings, 0 replies; 16+ messages in thread
From: Isaku Yamahata @ 2010-11-15 7:30 UTC (permalink / raw)
To: qemu-devel; +Cc: skandasa, adnan, wexu2, mst, yamahata, etmartin
remove unnecessary sizeof.
Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>
---
hw/pcie_regs.h | 2 ++
1 files changed, 2 insertions(+), 0 deletions(-)
diff --git a/hw/pcie_regs.h b/hw/pcie_regs.h
index 3461a1b..4d123d9 100644
--- a/hw/pcie_regs.h
+++ b/hw/pcie_regs.h
@@ -94,7 +94,9 @@
#define PCI_ERR_CAP_MHRE 0x00000400
#define PCI_ERR_CAP_TLP 0x00000800
+#define PCI_ERR_HEADER_LOG_SIZE 16
#define PCI_ERR_TLP_PREFIX_LOG 0x38
+#define PCI_ERR_TLP_PREFIX_LOG_SIZE 16
#define PCI_SEC_STATUS_RCV_SYSTEM_ERROR 0x4000
--
1.7.1.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [Qemu-devel] [PATCH v8 06/11] pcie/aer: helper functions for pcie aer capability
2010-11-15 7:30 [Qemu-devel] [PATCH v8 00/11] pcie port switch emulators Isaku Yamahata
` (4 preceding siblings ...)
2010-11-15 7:30 ` [Qemu-devel] [PATCH v8 05/11] pcie_regs.h: more constants Isaku Yamahata
@ 2010-11-15 7:30 ` Isaku Yamahata
2010-11-15 7:30 ` [Qemu-devel] [PATCH v8 07/11] pci: introduce a parser for pci device path Isaku Yamahata
` (4 subsequent siblings)
10 siblings, 0 replies; 16+ messages in thread
From: Isaku Yamahata @ 2010-11-15 7:30 UTC (permalink / raw)
To: qemu-devel; +Cc: skandasa, adnan, wexu2, mst, yamahata, etmartin
This patch implements helper functions for pcie aer capability
which will be used later.
Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>
---
Changes v7 -> v8:
- various changes to follow the review.
- s/TLP_PRESENT/TLP_PREFIX_PRESENT/g
Changes v6 -> v7:
- make error log buffer non-ringed buffer
- refactor pcie_aer_error_inject()
- clean up of pcie_aer_write_config()
- make pcie_aer_inject_error() return error
- remove AERMsgResult
- remove PCIEAERSeverity
- reduce forward declarations
- style clean ups
- remove paren for sizeof.
Chnages v5 -> v6:
- cleaned up pcie_aer_write_config().
- enum definition.
Changes v4 -> v5:
- use pci_xxx_test_and_xxx_mask()
- rewrote PCIDevice::written bits.
- eliminated pcie_aer_notify()
- introduced PCIExpressDevice::aer_intx
Changes v3 -> v4:
- various naming fixes.
- use pci bit operation helper function
- eliminate errmsg function pointer
- replace pci_shift_xxx() with PCIDevice::written
- uncorrect error status register.
- dropped pcie_aer_cap()
Changes v2 -> v3:
- split out from pcie.[ch] to pcie_aer.[ch] to make the files sorter.
- embeded PCIExpressDevice into PCIDevice.
- CodingStyle fix
---
Makefile.objs | 2 +-
hw/pcie.h | 14 +
hw/pcie_aer.c | 826 +++++++++++++++++++++++++++++++++++++++++++++++++++++++++
hw/pcie_aer.h | 106 ++++++++
qemu-common.h | 3 +
5 files changed, 950 insertions(+), 1 deletions(-)
create mode 100644 hw/pcie_aer.c
create mode 100644 hw/pcie_aer.h
diff --git a/Makefile.objs b/Makefile.objs
index 15569af..6f01220 100644
--- a/Makefile.objs
+++ b/Makefile.objs
@@ -208,7 +208,7 @@ hw-obj-$(CONFIG_PIIX4) += piix4.o
# PCI watchdog devices
hw-obj-y += wdt_i6300esb.o
-hw-obj-y += pcie.o pcie_port.o
+hw-obj-y += pcie.o pcie_aer.o pcie_port.o
hw-obj-y += msix.o msi.o
# PCI network cards
diff --git a/hw/pcie.h b/hw/pcie.h
index 8708504..7baa813 100644
--- a/hw/pcie.h
+++ b/hw/pcie.h
@@ -24,6 +24,7 @@
#include "hw.h"
#include "pci_regs.h"
#include "pcie_regs.h"
+#include "pcie_aer.h"
typedef enum {
/* for attention and power indicator */
@@ -79,6 +80,19 @@ struct PCIExpressDevice {
Software Notification of Hot-Plug Events, an interrupt
is sent whenever the logical and of these conditions
transitions from false to true. */
+
+ /* AER */
+ uint16_t aer_cap;
+ PCIEAERLog aer_log;
+ unsigned int aer_intx; /* INTx for error reporting
+ * default is 0 = INTA#
+ * If the chip wants to use other interrupt
+ * line, initialize this member with the
+ * desired number.
+ * If the chip dynamically changes this member,
+ * also initialize it when loaded as
+ * appropreately.
+ */
};
/* PCI express capability helper functions */
diff --git a/hw/pcie_aer.c b/hw/pcie_aer.c
new file mode 100644
index 0000000..0aabdb3
--- /dev/null
+++ b/hw/pcie_aer.c
@@ -0,0 +1,826 @@
+/*
+ * pcie_aer.c
+ *
+ * Copyright (c) 2010 Isaku Yamahata <yamahata at valinux co jp>
+ * VA Linux Systems Japan K.K.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#include "sysemu.h"
+#include "pci_bridge.h"
+#include "pcie.h"
+#include "msix.h"
+#include "msi.h"
+#include "pci_internals.h"
+#include "pcie_regs.h"
+
+//#define DEBUG_PCIE
+#ifdef DEBUG_PCIE
+# define PCIE_DPRINTF(fmt, ...) \
+ fprintf(stderr, "%s:%d " fmt, __func__, __LINE__, ## __VA_ARGS__)
+#else
+# define PCIE_DPRINTF(fmt, ...) do {} while (0)
+#endif
+#define PCIE_DEV_PRINTF(dev, fmt, ...) \
+ PCIE_DPRINTF("%s:%x "fmt, (dev)->name, (dev)->devfn, ## __VA_ARGS__)
+
+/* From 6.2.7 Error Listing and Rules. Table 6-2, 6-3 and 6-4 */
+static uint32_t pcie_aer_uncor_default_severity(uint32_t status)
+{
+ switch (status) {
+ case PCI_ERR_UNC_INTN:
+ case PCI_ERR_UNC_DLP:
+ case PCI_ERR_UNC_SDN:
+ case PCI_ERR_UNC_RX_OVER:
+ case PCI_ERR_UNC_FCP:
+ case PCI_ERR_UNC_MALF_TLP:
+ return PCI_ERR_ROOT_CMD_FATAL_EN;
+ case PCI_ERR_UNC_POISON_TLP:
+ case PCI_ERR_UNC_ECRC:
+ case PCI_ERR_UNC_UNSUP:
+ case PCI_ERR_UNC_COMP_TIME:
+ case PCI_ERR_UNC_COMP_ABORT:
+ case PCI_ERR_UNC_UNX_COMP:
+ case PCI_ERR_UNC_ACSV:
+ case PCI_ERR_UNC_MCBTLP:
+ case PCI_ERR_UNC_ATOP_EBLOCKED:
+ case PCI_ERR_UNC_TLP_PRF_BLOCKED:
+ return PCI_ERR_ROOT_CMD_NONFATAL_EN;
+ default:
+ abort();
+ break;
+ }
+ return PCI_ERR_ROOT_CMD_FATAL_EN;
+}
+
+static int aer_log_add_err(PCIEAERLog *aer_log, const PCIEAERErr *err)
+{
+ if (aer_log->log_num == aer_log->log_max) {
+ return -1;
+ }
+ memcpy(&aer_log->log[aer_log->log_num], err, sizeof *err);
+ aer_log->log_num++;
+ return 0;
+}
+
+static void aer_log_del_err(PCIEAERLog *aer_log, PCIEAERErr *err)
+{
+ assert(aer_log->log_num);
+ *err = aer_log->log[0];
+ aer_log->log_num--;
+ memmove(&aer_log->log[0], &aer_log->log[1],
+ aer_log->log_num * sizeof *err);
+}
+
+static void aer_log_clear_all_err(PCIEAERLog *aer_log)
+{
+ aer_log->log_num = 0;
+}
+
+void pcie_aer_init(PCIDevice *dev, uint16_t offset)
+{
+ PCIExpressDevice *exp;
+
+ pcie_add_capability(dev, PCI_EXT_CAP_ID_ERR, PCI_ERR_VER,
+ offset, PCI_ERR_SIZEOF);
+ exp = &dev->exp;
+ exp->aer_cap = offset;
+
+ /* log_max is property */
+ if (dev->exp.aer_log.log_max == PCIE_AER_LOG_MAX_UNSET) {
+ dev->exp.aer_log.log_max = PCIE_AER_LOG_MAX_DEFAULT;
+ }
+ /* clip down the value to avoid unreasobale memory usage */
+ if (dev->exp.aer_log.log_max > PCIE_AER_LOG_MAX_LIMIT) {
+ dev->exp.aer_log.log_max = PCIE_AER_LOG_MAX_LIMIT;
+ }
+ dev->exp.aer_log.log = qemu_mallocz(sizeof dev->exp.aer_log.log[0] *
+ dev->exp.aer_log.log_max);
+
+ pci_set_long(dev->w1cmask + offset + PCI_ERR_UNCOR_STATUS,
+ PCI_ERR_UNC_SUPPORTED);
+
+ pci_set_long(dev->config + offset + PCI_ERR_UNCOR_SEVER,
+ PCI_ERR_UNC_SEVERITY_DEFAULT);
+ pci_set_long(dev->wmask + offset + PCI_ERR_UNCOR_SEVER,
+ PCI_ERR_UNC_SUPPORTED);
+
+ pci_long_test_and_set_mask(dev->w1cmask + offset + PCI_ERR_COR_STATUS,
+ PCI_ERR_COR_STATUS);
+
+ pci_set_long(dev->config + offset + PCI_ERR_COR_MASK,
+ PCI_ERR_COR_MASK_DEFAULT);
+ pci_set_long(dev->wmask + offset + PCI_ERR_COR_MASK,
+ PCI_ERR_COR_SUPPORTED);
+
+ /* capabilities and control. multiple header logging is supported */
+ if (dev->exp.aer_log.log_max > 0) {
+ pci_set_long(dev->config + offset + PCI_ERR_CAP,
+ PCI_ERR_CAP_ECRC_GENC | PCI_ERR_CAP_ECRC_CHKC |
+ PCI_ERR_CAP_MHRC);
+ pci_set_long(dev->wmask + offset + PCI_ERR_CAP,
+ PCI_ERR_CAP_ECRC_GENE | PCI_ERR_CAP_ECRC_CHKE |
+ PCI_ERR_CAP_MHRE);
+ } else {
+ pci_set_long(dev->config + offset + PCI_ERR_CAP,
+ PCI_ERR_CAP_ECRC_GENC | PCI_ERR_CAP_ECRC_CHKC);
+ pci_set_long(dev->wmask + offset + PCI_ERR_CAP,
+ PCI_ERR_CAP_ECRC_GENE | PCI_ERR_CAP_ECRC_CHKE);
+ }
+
+ switch (pcie_cap_get_type(dev)) {
+ case PCI_EXP_TYPE_ROOT_PORT:
+ /* this case will be set by pcie_aer_root_init() */
+ /* fallthrough */
+ case PCI_EXP_TYPE_DOWNSTREAM:
+ case PCI_EXP_TYPE_UPSTREAM:
+ pci_word_test_and_set_mask(dev->wmask + PCI_BRIDGE_CONTROL,
+ PCI_BRIDGE_CTL_SERR);
+ pci_long_test_and_set_mask(dev->w1cmask + PCI_STATUS,
+ PCI_SEC_STATUS_RCV_SYSTEM_ERROR);
+ break;
+ default:
+ /* nothing */
+ break;
+ }
+}
+
+void pcie_aer_exit(PCIDevice *dev)
+{
+ qemu_free(dev->exp.aer_log.log);
+}
+
+static void pcie_aer_update_uncor_status(PCIDevice *dev)
+{
+ uint8_t *aer_cap = dev->config + dev->exp.aer_cap;
+ PCIEAERLog *aer_log = &dev->exp.aer_log;
+
+ uint16_t i;
+ for (i = 0; i < aer_log->log_num; i++) {
+ pci_long_test_and_set_mask(aer_cap + PCI_ERR_UNCOR_STATUS,
+ dev->exp.aer_log.log[i].status);
+ }
+}
+
+/*
+ * pcie_aer_msg() is called recursively by
+ * pcie_aer_msg_alldev(), pci_aer_msg_vbridge() and pcie_aer_msg_root_port()
+ */
+static void pcie_aer_msg(PCIDevice *dev, const PCIEAERMsg *msg);
+
+/*
+ * return value:
+ * true: error message is sent up
+ * false: error message is masked
+ *
+ * 6.2.6 Error Message Control
+ * Figure 6-3
+ * all pci express devices part
+ */
+static bool
+pcie_aer_msg_alldev(PCIDevice *dev, const PCIEAERMsg *msg)
+{
+ PCIDevice *parent_port;
+
+ if (!(pcie_aer_msg_is_uncor(msg) &&
+ (pci_get_word(dev->config + PCI_COMMAND) & PCI_COMMAND_SERR))) {
+ return false;
+ }
+
+ /* Signaled System Error
+ *
+ * 7.5.1.1 Command register
+ * Bit 8 SERR# Enable
+ *
+ * When Set, this bit enables reporting of Non-fatal and Fatal
+ * errors detected by the Function to the Root Complex. Note that
+ * errors are reported if enabled either through this bit or through
+ * the PCI Express specific bits in the Device Control register (see
+ * Section 7.8.4).
+ */
+ pci_word_test_and_set_mask(dev->config + PCI_STATUS,
+ PCI_STATUS_SIG_SYSTEM_ERROR);
+
+ if (!(msg->severity &
+ pci_get_word(dev->config + dev->exp.exp_cap + PCI_EXP_DEVCTL))) {
+ return false;
+ }
+
+ /* send up error message */
+ if (pci_is_express(dev) &&
+ pcie_cap_get_type(dev) == PCI_EXP_TYPE_ROOT_PORT) {
+ /* Root port notify system itself,
+ or send the error message to root complex event collector. */
+ /*
+ * if root port is associated to event collector, set
+ * parent_port = root complex event collector
+ * For now root complex event collector isn't supported.
+ */
+ parent_port = NULL;
+ } else {
+ parent_port = pci_bridge_get_device(dev->bus);
+ }
+ if (parent_port) {
+ if (!pci_is_express(parent_port)) {
+ /* just ignore it */
+ return false;
+ }
+ pcie_aer_msg(parent_port, msg);
+ }
+ return true;
+}
+
+/*
+ * return value:
+ * true: error message is sent up
+ * false: error message is masked
+ *
+ * 6.2.6 Error Message Control
+ * Figure 6-3
+ * virtual pci bridge part
+ */
+static bool pcie_aer_msg_vbridge(PCIDevice *dev, const PCIEAERMsg *msg)
+{
+ uint16_t bridge_control = pci_get_word(dev->config + PCI_BRIDGE_CONTROL);
+
+ if (pcie_aer_msg_is_uncor(msg)) {
+ /* Received System Error */
+ pci_word_test_and_set_mask(dev->config + PCI_SEC_STATUS,
+ PCI_SEC_STATUS_RCV_SYSTEM_ERROR);
+ }
+
+ if (!(bridge_control & PCI_BRIDGE_CTL_SERR)) {
+ return false;
+ }
+ return true;
+}
+
+void pcie_aer_root_set_vector(PCIDevice *dev, unsigned int vector)
+{
+ uint8_t *aer_cap = dev->config + dev->exp.aer_cap;
+ assert(vector < PCI_ERR_ROOT_IRQ_MAX);
+ pci_long_test_and_clear_mask(aer_cap + PCI_ERR_ROOT_STATUS,
+ PCI_ERR_ROOT_IRQ);
+ pci_long_test_and_set_mask(aer_cap + PCI_ERR_ROOT_STATUS,
+ vector << PCI_ERR_ROOT_IRQ_SHIFT);
+}
+
+static unsigned int pcie_aer_root_get_vector(PCIDevice *dev)
+{
+ uint8_t *aer_cap = dev->config + dev->exp.aer_cap;
+ uint32_t root_status = pci_get_long(aer_cap + PCI_ERR_ROOT_STATUS);
+ return (root_status & PCI_ERR_ROOT_IRQ) >> PCI_ERR_ROOT_IRQ_SHIFT;
+}
+
+/*
+ * return value:
+ * true: error message is sent up
+ * false: error message is masked
+ *
+ * 6.2.6 Error Message Control
+ * Figure 6-3
+ * root port part
+ */
+static bool pcie_aer_msg_root_port(PCIDevice *dev, const PCIEAERMsg *msg)
+{
+ bool msg_sent;
+ uint16_t cmd;
+ uint8_t *aer_cap;
+ uint32_t root_cmd;
+ uint32_t root_status;
+ bool msi_trigger;
+
+ msg_sent = false;
+ cmd = pci_get_word(dev->config + PCI_COMMAND);
+ aer_cap = dev->config + dev->exp.aer_cap;
+ root_cmd = pci_get_long(aer_cap + PCI_ERR_ROOT_COMMAND);
+ root_status = pci_get_long(aer_cap + PCI_ERR_ROOT_STATUS);
+ msi_trigger = false;
+
+ if (cmd & PCI_COMMAND_SERR) {
+ /* System Error.
+ *
+ * The way to report System Error is platform specific and
+ * it isn't implemented in qemu right now.
+ * So just discard the error for now.
+ * OS which cares of aer would receive errors via
+ * native aer mechanims, so this wouldn't matter.
+ */
+ }
+
+ /* Errro Message Received: Root Error Status register */
+ switch (msg->severity) {
+ case PCI_ERR_ROOT_CMD_COR_EN:
+ if (root_status & PCI_ERR_ROOT_COR_RCV) {
+ root_status |= PCI_ERR_ROOT_MULTI_COR_RCV;
+ } else {
+ if (root_cmd & PCI_ERR_ROOT_CMD_COR_EN) {
+ msi_trigger = true;
+ }
+ pci_set_word(aer_cap + PCI_ERR_ROOT_COR_SRC, msg->source_id);
+ }
+ root_status |= PCI_ERR_ROOT_COR_RCV;
+ break;
+ case PCI_ERR_ROOT_CMD_NONFATAL_EN:
+ if (!(root_status & PCI_ERR_ROOT_NONFATAL_RCV) &&
+ root_cmd & PCI_ERR_ROOT_CMD_NONFATAL_EN) {
+ msi_trigger = true;
+ }
+ root_status |= PCI_ERR_ROOT_NONFATAL_RCV;
+ break;
+ case PCI_ERR_ROOT_CMD_FATAL_EN:
+ if (!(root_status & PCI_ERR_ROOT_FATAL_RCV) &&
+ root_cmd & PCI_ERR_ROOT_CMD_FATAL_EN) {
+ msi_trigger = true;
+ }
+ if (!(root_status & PCI_ERR_ROOT_UNCOR_RCV)) {
+ root_status |= PCI_ERR_ROOT_FIRST_FATAL;
+ }
+ root_status |= PCI_ERR_ROOT_FATAL_RCV;
+ break;
+ default:
+ abort();
+ break;
+ }
+ if (pcie_aer_msg_is_uncor(msg)) {
+ if (root_status & PCI_ERR_ROOT_UNCOR_RCV) {
+ root_status |= PCI_ERR_ROOT_MULTI_UNCOR_RCV;
+ } else {
+ pci_set_word(aer_cap + PCI_ERR_ROOT_SRC, msg->source_id);
+ }
+ root_status |= PCI_ERR_ROOT_UNCOR_RCV;
+ }
+ pci_set_long(aer_cap + PCI_ERR_ROOT_STATUS, root_status);
+
+ if (root_cmd & msg->severity) {
+ /* 6.2.4.1.2 Interrupt Generation */
+ if (pci_msi_enabled(dev)) {
+ if (msi_trigger) {
+ pci_msi_notify(dev, pcie_aer_root_get_vector(dev));
+ }
+ } else {
+ qemu_set_irq(dev->irq[dev->exp.aer_intx], 1);
+ }
+ msg_sent = true;
+ }
+ return msg_sent;
+}
+
+/*
+ * 6.2.6 Error Message Control Figure 6-3
+ */
+static void pcie_aer_msg(PCIDevice *dev, const PCIEAERMsg *msg)
+{
+ uint8_t type;
+ bool msg_sent;
+
+ assert(pci_is_express(dev));
+
+ type = pcie_cap_get_type(dev);
+ if (type == PCI_EXP_TYPE_ROOT_PORT ||
+ type == PCI_EXP_TYPE_UPSTREAM ||
+ type == PCI_EXP_TYPE_DOWNSTREAM) {
+ msg_sent = pcie_aer_msg_vbridge(dev, msg);
+ if (!msg_sent) {
+ return;
+ }
+ }
+ msg_sent = pcie_aer_msg_alldev(dev, msg);
+ if (type == PCI_EXP_TYPE_ROOT_PORT && msg_sent) {
+ pcie_aer_msg_root_port(dev, msg);
+ }
+}
+
+static void pcie_aer_update_log(PCIDevice *dev, const PCIEAERErr *err)
+{
+ uint8_t *aer_cap = dev->config + dev->exp.aer_cap;
+ uint8_t first_bit = ffsl(err->status) - 1;
+ uint32_t errcap = pci_get_long(aer_cap + PCI_ERR_CAP);
+ int i;
+
+ assert(err->status);
+ assert(err->status & (err->status - 1));
+
+ errcap &= ~(PCI_ERR_CAP_FEP_MASK | PCI_ERR_CAP_TLP);
+ errcap |= PCI_ERR_CAP_FEP(first_bit);
+
+ if (err->flags & PCIE_AER_ERR_HEADER_VALID) {
+ for (i = 0; i < ARRAY_SIZE(err->header); ++i) {
+ /* 7.10.8 Header Log Register */
+ uint8_t *header_log =
+ aer_cap + PCI_ERR_HEADER_LOG + i * sizeof err->header[0];
+ cpu_to_be32wu((uint32_t*)header_log, err->header[i]);
+ }
+ } else {
+ assert(!(err->flags & PCIE_AER_ERR_TLP_PREFIX_PRESENT));
+ memset(aer_cap + PCI_ERR_HEADER_LOG, 0, PCI_ERR_HEADER_LOG_SIZE);
+ }
+
+ if ((err->flags & PCIE_AER_ERR_TLP_PREFIX_PRESENT) &&
+ (pci_get_long(dev->config + dev->exp.exp_cap + PCI_EXP_DEVCTL2) &
+ PCI_EXP_DEVCAP2_EETLPP)) {
+ for (i = 0; i < ARRAY_SIZE(err->prefix); ++i) {
+ /* 7.10.12 tlp prefix log register */
+ uint8_t *prefix_log =
+ aer_cap + PCI_ERR_TLP_PREFIX_LOG + i * sizeof err->prefix[0];
+ cpu_to_be32wu((uint32_t*)prefix_log, err->prefix[i]);
+ }
+ errcap |= PCI_ERR_CAP_TLP;
+ } else {
+ memset(aer_cap + PCI_ERR_TLP_PREFIX_LOG, 0,
+ PCI_ERR_TLP_PREFIX_LOG_SIZE);
+ }
+ pci_set_long(aer_cap + PCI_ERR_CAP, errcap);
+}
+
+static void pcie_aer_clear_log(PCIDevice *dev)
+{
+ uint8_t *aer_cap = dev->config + dev->exp.aer_cap;
+
+ pci_long_test_and_clear_mask(aer_cap + PCI_ERR_CAP,
+ PCI_ERR_CAP_FEP_MASK | PCI_ERR_CAP_TLP);
+
+ memset(aer_cap + PCI_ERR_HEADER_LOG, 0, PCI_ERR_HEADER_LOG_SIZE);
+ memset(aer_cap + PCI_ERR_TLP_PREFIX_LOG, 0, PCI_ERR_TLP_PREFIX_LOG_SIZE);
+}
+
+static void pcie_aer_clear_error(PCIDevice *dev)
+{
+ uint8_t *aer_cap = dev->config + dev->exp.aer_cap;
+ uint32_t errcap = pci_get_long(aer_cap + PCI_ERR_CAP);
+ PCIEAERLog *aer_log = &dev->exp.aer_log;
+ PCIEAERErr err;
+
+ if (!(errcap & PCI_ERR_CAP_MHRE) || !aer_log->log_num) {
+ pcie_aer_clear_log(dev);
+ return;
+ }
+
+ /*
+ * If more errors are queued, set corresponding bits in uncorrectable
+ * error status.
+ * We emulate uncorrectable error status register as W1CS.
+ * So set bit in uncorrectable error status here again for multiple
+ * error recording support.
+ *
+ * 6.2.4.2 Multiple Error Handling(Advanced Error Reporting Capability)
+ */
+ pcie_aer_update_uncor_status(dev);
+
+ aer_log_del_err(aer_log, &err);
+ pcie_aer_update_log(dev, &err);
+}
+
+static int pcie_aer_record_error(PCIDevice *dev,
+ const PCIEAERErr *err)
+{
+ uint8_t *aer_cap = dev->config + dev->exp.aer_cap;
+ uint32_t errcap = pci_get_long(aer_cap + PCI_ERR_CAP);
+ int fep = PCI_ERR_CAP_FEP(errcap);
+
+ assert(err->status);
+ assert(err->status & (err->status - 1));
+
+ if (errcap & PCI_ERR_CAP_MHRE &&
+ (pci_get_long(aer_cap + PCI_ERR_UNCOR_STATUS) & (1U << fep))) {
+ /* Not first error. queue error */
+ if (aer_log_add_err(&dev->exp.aer_log, err) < 0) {
+ /* overflow */
+ return -1;
+ }
+ return 0;
+ }
+
+ pcie_aer_update_log(dev, err);
+ return 0;
+}
+
+typedef struct PCIEAERInject {
+ PCIDevice *dev;
+ uint8_t *aer_cap;
+ const PCIEAERErr *err;
+ uint16_t devctl;
+ uint16_t devsta;
+ uint32_t error_status;
+ bool unsupported_request;
+ bool log_overflow;
+ PCIEAERMsg msg;
+} PCIEAERInject;
+
+static bool pcie_aer_inject_cor_error(PCIEAERInject *inj,
+ uint32_t uncor_status,
+ bool is_advisory_nonfatal)
+{
+ PCIDevice *dev = inj->dev;
+
+ inj->devsta |= PCI_EXP_DEVSTA_CED;
+ if (inj->unsupported_request) {
+ inj->devsta |= PCI_EXP_DEVSTA_URD;
+ }
+ pci_set_word(dev->config + dev->exp.exp_cap + PCI_EXP_DEVSTA, inj->devsta);
+
+ if (inj->aer_cap) {
+ uint32_t mask;
+ pci_long_test_and_set_mask(inj->aer_cap + PCI_ERR_COR_STATUS,
+ inj->error_status);
+ mask = pci_get_long(inj->aer_cap + PCI_ERR_COR_MASK);
+ if (mask & inj->error_status) {
+ return false;
+ }
+ if (is_advisory_nonfatal) {
+ uint32_t uncor_mask =
+ pci_get_long(inj->aer_cap + PCI_ERR_UNCOR_MASK);
+ if (!(uncor_mask & uncor_status)) {
+ inj->log_overflow = !!pcie_aer_record_error(dev, inj->err);
+ }
+ pci_long_test_and_set_mask(inj->aer_cap + PCI_ERR_UNCOR_STATUS,
+ uncor_status);
+ }
+ }
+
+ if (inj->unsupported_request && !(inj->devctl & PCI_EXP_DEVCTL_URRE)) {
+ return false;
+ }
+ if (!(inj->devctl & PCI_EXP_DEVCTL_CERE)) {
+ return false;
+ }
+
+ inj->msg.severity = PCI_ERR_ROOT_CMD_COR_EN;
+ return true;
+}
+
+static bool pcie_aer_inject_uncor_error(PCIEAERInject *inj, bool is_fatal)
+{
+ PCIDevice *dev = inj->dev;
+ uint16_t cmd;
+
+ if (is_fatal) {
+ inj->devsta |= PCI_EXP_DEVSTA_FED;
+ } else {
+ inj->devsta |= PCI_EXP_DEVSTA_NFED;
+ }
+ if (inj->unsupported_request) {
+ inj->devsta |= PCI_EXP_DEVSTA_URD;
+ }
+ pci_set_long(dev->config + dev->exp.exp_cap + PCI_EXP_DEVSTA, inj->devsta);
+
+ if (inj->aer_cap) {
+ uint32_t mask = pci_get_long(inj->aer_cap + PCI_ERR_UNCOR_MASK);
+ if (mask & inj->error_status) {
+ pci_long_test_and_set_mask(inj->aer_cap + PCI_ERR_UNCOR_STATUS,
+ inj->error_status);
+ return false;
+ }
+
+ inj->log_overflow = !!pcie_aer_record_error(dev, inj->err);
+ pci_long_test_and_set_mask(inj->aer_cap + PCI_ERR_UNCOR_STATUS,
+ inj->error_status);
+ }
+
+ cmd = pci_get_word(dev->config + PCI_COMMAND);
+ if (inj->unsupported_request &&
+ !(inj->devctl & PCI_EXP_DEVCTL_URRE) && !(cmd & PCI_COMMAND_SERR)) {
+ return false;
+ }
+ if (is_fatal) {
+ if (!((cmd & PCI_COMMAND_SERR) ||
+ (inj->devctl & PCI_EXP_DEVCTL_FERE))) {
+ return false;
+ }
+ inj->msg.severity = PCI_ERR_ROOT_CMD_FATAL_EN;
+ } else {
+ if (!((cmd & PCI_COMMAND_SERR) ||
+ (inj->devctl & PCI_EXP_DEVCTL_NFERE))) {
+ return false;
+ }
+ inj->msg.severity = PCI_ERR_ROOT_CMD_NONFATAL_EN;
+ }
+ return true;
+}
+
+/*
+ * non-Function specific error must be recorded in all functions.
+ * It is the responsibility of the caller of this function.
+ * It is also caller's responsiblity to determine which function should
+ * report the rerror.
+ *
+ * 6.2.4 Error Logging
+ * 6.2.5 Sqeunce of Device Error Signaling and Logging Operations
+ * table 6-2: Flowchard Showing Sequence of Device Error Signaling and Logging
+ * Operations
+ */
+int pcie_aer_inject_error(PCIDevice *dev, const PCIEAERErr *err)
+{
+ uint8_t *aer_cap = NULL;
+ uint16_t devctl = 0;
+ uint16_t devsta = 0;
+ uint32_t error_status = err->status;
+ PCIEAERInject inj;
+
+ if (!pci_is_express(dev)) {
+ return -1;
+ }
+
+ if (err->flags & PCIE_AER_ERR_IS_CORRECTABLE) {
+ error_status &= PCI_ERR_COR_SUPPORTED;
+ } else {
+ error_status &= PCI_ERR_UNC_SUPPORTED;
+ }
+
+ /* invalid status bit. one and only one bit must be set */
+ if (!error_status || (error_status & (error_status - 1))) {
+ return -1;
+ }
+
+ if (dev->exp.aer_cap) {
+ uint8_t *exp_cap = dev->config + dev->exp.exp_cap;
+ aer_cap = dev->config + dev->exp.aer_cap;
+ devctl = pci_get_long(exp_cap + PCI_EXP_DEVCTL);
+ devsta = pci_get_long(exp_cap + PCI_EXP_DEVSTA);
+ }
+
+ inj.dev = dev;
+ inj.aer_cap = aer_cap;
+ inj.err = err;
+ inj.devctl = devctl;
+ inj.devsta = devsta;
+ inj.error_status = error_status;
+ inj.unsupported_request = !(err->flags & PCIE_AER_ERR_IS_CORRECTABLE) &&
+ err->status == PCI_ERR_UNC_UNSUP;
+ inj.log_overflow = false;
+
+ if (err->flags & PCIE_AER_ERR_IS_CORRECTABLE) {
+ if (!pcie_aer_inject_cor_error(&inj, 0, false)) {
+ return 0;
+ }
+ } else {
+ bool is_fatal =
+ pcie_aer_uncor_default_severity(error_status) ==
+ PCI_ERR_ROOT_CMD_FATAL_EN;
+ if (aer_cap) {
+ is_fatal =
+ error_status & pci_get_long(aer_cap + PCI_ERR_UNCOR_SEVER);
+ }
+ if (!is_fatal && (err->flags & PCIE_AER_ERR_MAYBE_ADVISORY)) {
+ inj.error_status = PCI_ERR_COR_ADV_NONFATAL;
+ if (!pcie_aer_inject_cor_error(&inj, error_status, true)) {
+ return 0;
+ }
+ } else {
+ if (!pcie_aer_inject_uncor_error(&inj, is_fatal)) {
+ return 0;
+ }
+ }
+ }
+
+ /* send up error message */
+ inj.msg.source_id = err->source_id;
+ pcie_aer_msg(dev, &inj.msg);
+
+ if (inj.log_overflow) {
+ PCIEAERErr header_log_overflow = {
+ .status = PCI_ERR_COR_HL_OVERFLOW,
+ .flags = PCIE_AER_ERR_IS_CORRECTABLE,
+ };
+ int ret = pcie_aer_inject_error(dev, &header_log_overflow);
+ assert(!ret);
+ }
+ return 0;
+}
+
+void pcie_aer_write_config(PCIDevice *dev,
+ uint32_t addr, uint32_t val, int len)
+{
+ uint8_t *aer_cap = dev->config + dev->exp.aer_cap;
+ uint32_t errcap = pci_get_long(aer_cap + PCI_ERR_CAP);
+ uint32_t first_error = 1U << PCI_ERR_CAP_FEP(errcap);
+ uint32_t uncorsta = pci_get_long(aer_cap + PCI_ERR_UNCOR_STATUS);
+
+ /* uncorrectable error */
+ if (!(uncorsta & first_error)) {
+ /* the bit that corresponds to the first error is cleared */
+ pcie_aer_clear_error(dev);
+ } else if (errcap & PCI_ERR_CAP_MHRE) {
+ /* When PCI_ERR_CAP_MHRE is enabled and the first error isn't cleared
+ * nothing should happen. So we have to revert the modification to
+ * the register.
+ */
+ pcie_aer_update_uncor_status(dev);
+ } else {
+ /* capability & control
+ * PCI_ERR_CAP_MHRE might be cleared, so clear of header log.
+ */
+ aer_log_clear_all_err(&dev->exp.aer_log);
+ }
+}
+
+void pcie_aer_root_init(PCIDevice *dev)
+{
+ uint16_t pos = dev->exp.aer_cap;
+
+ pci_set_long(dev->wmask + pos + PCI_ERR_ROOT_COMMAND,
+ PCI_ERR_ROOT_CMD_EN_MASK);
+ pci_set_long(dev->w1cmask + pos + PCI_ERR_ROOT_STATUS,
+ PCI_ERR_ROOT_STATUS_REPORT_MASK);
+}
+
+void pcie_aer_root_reset(PCIDevice *dev)
+{
+ uint8_t* aer_cap = dev->config + dev->exp.aer_cap;
+
+ pci_set_long(aer_cap + PCI_ERR_ROOT_COMMAND, 0);
+
+ /*
+ * Advanced Error Interrupt Message Number in Root Error Status Register
+ * must be updated by chip dependent code because it's chip dependent
+ * which number is used.
+ */
+}
+
+static bool pcie_aer_root_does_trigger(uint32_t cmd, uint32_t status)
+{
+ return
+ ((cmd & PCI_ERR_ROOT_CMD_COR_EN) && (status & PCI_ERR_ROOT_COR_RCV)) ||
+ ((cmd & PCI_ERR_ROOT_CMD_NONFATAL_EN) &&
+ (status & PCI_ERR_ROOT_NONFATAL_RCV)) ||
+ ((cmd & PCI_ERR_ROOT_CMD_FATAL_EN) &&
+ (status & PCI_ERR_ROOT_FATAL_RCV));
+}
+
+void pcie_aer_root_write_config(PCIDevice *dev,
+ uint32_t addr, uint32_t val, int len,
+ uint32_t root_cmd_prev)
+{
+ uint8_t *aer_cap = dev->config + dev->exp.aer_cap;
+
+ /* root command register */
+ uint32_t root_cmd = pci_get_long(aer_cap + PCI_ERR_ROOT_COMMAND);
+ if (root_cmd & PCI_ERR_ROOT_CMD_EN_MASK) {
+ /* 6.2.4.1.2 Interrupt Generation */
+
+ /* 0 -> 1 */
+ uint32_t root_cmd_set = (root_cmd_prev ^ root_cmd) & root_cmd;
+ uint32_t root_status = pci_get_long(aer_cap + PCI_ERR_ROOT_STATUS);
+
+ if (pci_msi_enabled(dev)) {
+ if (pcie_aer_root_does_trigger(root_cmd_set, root_status)) {
+ pci_msi_notify(dev, pcie_aer_root_get_vector(dev));
+ }
+ } else {
+ int int_level = pcie_aer_root_does_trigger(root_cmd, root_status);
+ qemu_set_irq(dev->irq[dev->exp.aer_intx], int_level);
+ }
+ }
+}
+
+static const VMStateDescription vmstate_pcie_aer_err = {
+ .name = "PCIE_AER_ERROR",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .minimum_version_id_old = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT32(status, PCIEAERErr),
+ VMSTATE_UINT16(source_id, PCIEAERErr),
+ VMSTATE_UINT16(flags, PCIEAERErr),
+ VMSTATE_UINT32_ARRAY(header, PCIEAERErr, 4),
+ VMSTATE_UINT32_ARRAY(prefix, PCIEAERErr, 4),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
+#define VMSTATE_PCIE_AER_ERRS(_field, _state, _field_num, _vmsd, _type) { \
+ .name = (stringify(_field)), \
+ .version_id = 0, \
+ .num_offset = vmstate_offset_value(_state, _field_num, uint16_t), \
+ .size = sizeof(_type), \
+ .vmsd = &(_vmsd), \
+ .flags = VMS_POINTER | VMS_VARRAY_UINT16 | VMS_STRUCT, \
+ .offset = vmstate_offset_pointer(_state, _field, _type), \
+}
+
+const VMStateDescription vmstate_pcie_aer_log = {
+ .name = "PCIE_AER_ERROR_LOG",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .minimum_version_id_old = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINT16(log_num, PCIEAERLog),
+ VMSTATE_UINT16(log_max, PCIEAERLog),
+ VMSTATE_PCIE_AER_ERRS(log, PCIEAERLog, log_num,
+ vmstate_pcie_aer_err, PCIEAERErr),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
diff --git a/hw/pcie_aer.h b/hw/pcie_aer.h
new file mode 100644
index 0000000..3de7763
--- /dev/null
+++ b/hw/pcie_aer.h
@@ -0,0 +1,106 @@
+/*
+ * pcie_aer.h
+ *
+ * Copyright (c) 2010 Isaku Yamahata <yamahata at valinux co jp>
+ * VA Linux Systems Japan K.K.
+ *
+ * This program is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation; either version 2 of the License, or
+ * (at your option) any later version.
+ *
+ * This program is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+
+#ifndef QEMU_PCIE_AER_H
+#define QEMU_PCIE_AER_H
+
+#include "hw.h"
+
+/* definitions which PCIExpressDevice uses */
+
+/* AER log */
+struct PCIEAERLog {
+ /* This structure is saved/loaded.
+ So explicitly size them instead of unsigned int */
+
+ /* the number of currently recorded log in log member */
+ uint16_t log_num;
+
+ /*
+ * The maximum number of the log. Errors can be logged up to this.
+ *
+ * This is configurable property.
+ * The specified value will be clipped down to PCIE_AER_LOG_MAX_LIMIT
+ * to avoid unreasonable memory usage.
+ * I bet that 128 log size would be big enough, otherwise too many errors
+ * for system to function normaly. But could consecutive errors occur?
+ */
+#define PCIE_AER_LOG_MAX_DEFAULT 8
+#define PCIE_AER_LOG_MAX_LIMIT 128
+#define PCIE_AER_LOG_MAX_UNSET 0xffff
+ uint16_t log_max;
+
+ /* Error log. log_max-sized array */
+ PCIEAERErr *log;
+};
+
+/* aer error message: error signaling message has only error sevirity and
+ source id. See 2.2.8.3 error signaling messages */
+struct PCIEAERMsg {
+ /*
+ * PCI_ERR_ROOT_CMD_{COR, NONFATAL, FATAL}_EN
+ * = PCI_EXP_DEVCTL_{CERE, NFERE, FERE}
+ */
+ uint32_t severity;
+
+ uint16_t source_id; /* bdf */
+};
+
+static inline bool
+pcie_aer_msg_is_uncor(const PCIEAERMsg *msg)
+{
+ return msg->severity == PCI_ERR_ROOT_CMD_NONFATAL_EN ||
+ msg->severity == PCI_ERR_ROOT_CMD_FATAL_EN;
+}
+
+/* error */
+struct PCIEAERErr {
+ uint32_t status; /* error status bits */
+ uint16_t source_id; /* bdf */
+
+#define PCIE_AER_ERR_IS_CORRECTABLE 0x1 /* correctable/uncorrectable */
+#define PCIE_AER_ERR_MAYBE_ADVISORY 0x2 /* maybe advisory non-fatal */
+#define PCIE_AER_ERR_HEADER_VALID 0x4 /* TLP header is logged */
+#define PCIE_AER_ERR_TLP_PREFIX_PRESENT 0x8 /* TLP Prefix is logged */
+ uint16_t flags;
+
+ uint32_t header[4]; /* TLP header */
+ uint32_t prefix[4]; /* TLP header prefix */
+};
+
+extern const VMStateDescription vmstate_pcie_aer_log;
+
+void pcie_aer_init(PCIDevice *dev, uint16_t offset);
+void pcie_aer_exit(PCIDevice *dev);
+void pcie_aer_write_config(PCIDevice *dev,
+ uint32_t addr, uint32_t val, int len);
+
+/* aer root port */
+void pcie_aer_root_set_vector(PCIDevice *dev, unsigned int vector);
+void pcie_aer_root_init(PCIDevice *dev);
+void pcie_aer_root_reset(PCIDevice *dev);
+void pcie_aer_root_write_config(PCIDevice *dev,
+ uint32_t addr, uint32_t val, int len,
+ uint32_t root_cmd_prev);
+
+/* error injection */
+int pcie_aer_inject_error(PCIDevice *dev, const PCIEAERErr *err);
+
+#endif /* QEMU_PCIE_AER_H */
diff --git a/qemu-common.h b/qemu-common.h
index b3957f1..de82c2e 100644
--- a/qemu-common.h
+++ b/qemu-common.h
@@ -240,6 +240,9 @@ typedef struct PCIBus PCIBus;
typedef struct PCIDevice PCIDevice;
typedef struct PCIExpressDevice PCIExpressDevice;
typedef struct PCIBridge PCIBridge;
+typedef struct PCIEAERMsg PCIEAERMsg;
+typedef struct PCIEAERLog PCIEAERLog;
+typedef struct PCIEAERErr PCIEAERErr;
typedef struct PCIEPort PCIEPort;
typedef struct PCIESlot PCIESlot;
typedef struct SerialState SerialState;
--
1.7.1.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [Qemu-devel] [PATCH v8 07/11] pci: introduce a parser for pci device path
2010-11-15 7:30 [Qemu-devel] [PATCH v8 00/11] pcie port switch emulators Isaku Yamahata
` (5 preceding siblings ...)
2010-11-15 7:30 ` [Qemu-devel] [PATCH v8 06/11] pcie/aer: helper functions for pcie aer capability Isaku Yamahata
@ 2010-11-15 7:30 ` Isaku Yamahata
2010-11-15 8:06 ` [Qemu-devel] " Michael S. Tsirkin
2010-11-15 7:30 ` [Qemu-devel] [PATCH v8 08/11] pcie/aer: glue aer error injection into qemu monitor Isaku Yamahata
` (3 subsequent siblings)
10 siblings, 1 reply; 16+ messages in thread
From: Isaku Yamahata @ 2010-11-15 7:30 UTC (permalink / raw)
To: qemu-devel; +Cc: skandasa, adnan, wexu2, mst, yamahata, etmartin
introduce a function to parse pci device path of
the format, [Domain:]Slot.Function:Slot.Function....:Slot.Function.
Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>
---
hw/pci.c | 87 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
hw/pci.h | 1 +
2 files changed, 88 insertions(+), 0 deletions(-)
diff --git a/hw/pci.c b/hw/pci.c
index fba765b..6a9a5ef 100644
--- a/hw/pci.c
+++ b/hw/pci.c
@@ -433,6 +433,93 @@ static void pci_set_default_subsystem_id(PCIDevice *pci_dev)
}
/*
+ * Parse format [Domain:]Slot.Function:Slot.Function....:Slot.Function
+ * and get PCIDevice
+ * return 0 on success
+ * -1 on error: format is invalid or device isn't found.
+ */
+int pci_parse_dev_path(const char *addr, PCIDevice **pdev)
+{
+ unsigned long domain;
+ unsigned long slot;
+ unsigned long func;
+ const char *p;
+ char *e;
+ unsigned long val;
+ PCIBus *bus;
+ PCIBus *child_bus;
+ PCIDevice *d;
+
+ p = addr;
+ val = strtoul(p, &e, 0);
+ if (e == p) {
+ return -1;
+ }
+ if (*e == ':') {
+ domain = val;
+ p = e + 1;
+ val = strtoul(p, &e, 0);
+ if (e == p) {
+ return -1;
+ }
+ } else if (*e == '.'){
+ domain = 0;
+ } else {
+ return -1;
+ }
+ if (domain > 0xffff) {
+ return -1;
+ }
+
+ bus = pci_find_root_bus(domain);
+ if (!bus) {
+ return -1;
+ }
+
+ for (;;) {
+ slot = val;
+ if (*e != '.') {
+ return -1;
+ }
+ p = e + 1;
+ val = strtoul(p, &e, 0);
+ if (e == p) {
+ return -1;
+ }
+ func = val;
+ if (slot > 0x1f || func >= PCI_FUNC_MAX) {
+ return -1;
+ }
+ d = bus->devices[PCI_DEVFN(slot, func)];
+ if (!d) {
+ return -1;
+ }
+ if (*e == '\0') {
+ break;
+ }
+
+ if (*e != ':') {
+ return -1;
+ }
+ p = e + 1;
+ val = strtoul(p, &e, 0);
+ if (e == p) {
+ return -1;
+ }
+ QLIST_FOREACH(child_bus, &bus->child, sibling) {
+ if (child_bus->parent_dev == d) {
+ bus = child_bus;
+ continue;
+ }
+ }
+ return -1;
+ }
+
+ *pdev = d;
+ return 0;
+}
+
+/*
* Parse [[<domain>:]<bus>:]<slot>, return -1 on error if funcp == NULL
* [[<domain>:]<bus>:]<slot>.<func>, return -1 on error
*/
diff --git a/hw/pci.h b/hw/pci.h
index 7100804..8c16f91 100644
--- a/hw/pci.h
+++ b/hw/pci.h
@@ -239,6 +239,7 @@ PCIBus *pci_find_bus(PCIBus *bus, int bus_num);
PCIDevice *pci_find_device(PCIBus *bus, int bus_num, int slot, int function);
PCIBus *pci_get_bus_devfn(int *devfnp, const char *devaddr);
+int pci_parse_dev_path(const char *addr, PCIDevice **pdev);
int pci_parse_devaddr(const char *addr, int *domp, int *busp,
unsigned int *slotp, unsigned int *funcp);
int pci_read_devaddr(Monitor *mon, const char *addr, int *domp, int *busp,
--
1.7.1.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [Qemu-devel] [PATCH v8 08/11] pcie/aer: glue aer error injection into qemu monitor
2010-11-15 7:30 [Qemu-devel] [PATCH v8 00/11] pcie port switch emulators Isaku Yamahata
` (6 preceding siblings ...)
2010-11-15 7:30 ` [Qemu-devel] [PATCH v8 07/11] pci: introduce a parser for pci device path Isaku Yamahata
@ 2010-11-15 7:30 ` Isaku Yamahata
2010-11-15 7:30 ` [Qemu-devel] [PATCH v8 09/11] ioh3420: support aer Isaku Yamahata
` (2 subsequent siblings)
10 siblings, 0 replies; 16+ messages in thread
From: Isaku Yamahata @ 2010-11-15 7:30 UTC (permalink / raw)
To: qemu-devel; +Cc: skandasa, adnan, wexu2, mst, yamahata, etmartin
introduce pcie_aer_inject_error command.
Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>
---
Changes v7 -> v8:
- use domain:slot.func:slot.func...:slot.func instead of domain:bus:slot.func
- allow symbolic aer error name in addition to 32bit value
Changes v6 -> v7:
- check return value.
Changes v3 -> v4:
- s/PCIE_AER/PCIEAER/g for structure names.
- compilation adjustment.
Changes v2 -> v3:
- compilation adjustment.
pcie/aer/qmp: glue update
glue update.
Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>
pcie/aer: update glue function
update glue function.
Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>
---
hmp-commands.hx | 23 ++++++
hw/pcie_aer.c | 219 +++++++++++++++++++++++++++++++++++++++++++++++++++++++
sysemu.h | 5 +
3 files changed, 247 insertions(+), 0 deletions(-)
diff --git a/hmp-commands.hx b/hmp-commands.hx
index e5585ba..32b8d8d 100644
--- a/hmp-commands.hx
+++ b/hmp-commands.hx
@@ -836,6 +836,29 @@ Hot remove PCI device.
ETEXI
{
+ .name = "pcie_aer_inject_error",
+ .args_type = "advisory_non_fatal:-a,correctable:-c,"
+ "pci_dev_path:s,error_status:s,"
+ "header0:i?,header1:i?,header2:i?,header3:i?,"
+ "prefix0:i?,prefix1:i?,prefix2:i?,prefix3:i?",
+ .params = "[-a] [-c] [[<domain>:]<slot>.<func>:...:<slot>.<func> "
+ "<error status: error string or 32bit> "
+ "[<tlp header:(32bit x 4)>] "
+ "[<tlp header prefix:(32bit x 4)>]",
+ .help = "inject pcie aer error "
+ "(use -a for advisory non fatal error) "
+ "(use -c for correctable error)",
+ .user_print = pcie_aer_inject_error_print,
+ .mhandler.cmd_new = do_pcie_aer_inejct_error,
+ },
+
+STEXI
+@item pcie_aer_inject_error
+@findex pcie_aer_inject_error
+Inject PCIe AER error
+ETEXI
+
+ {
.name = "host_net_add",
.args_type = "device:s,opts:s?",
.params = "tap|user|socket|vde|dump [options]",
diff --git a/hw/pcie_aer.c b/hw/pcie_aer.c
index 0aabdb3..2d3991c 100644
--- a/hw/pcie_aer.c
+++ b/hw/pcie_aer.c
@@ -19,6 +19,8 @@
*/
#include "sysemu.h"
+#include "qemu-objects.h"
+#include "monitor.h"
#include "pci_bridge.h"
#include "pcie.h"
#include "msix.h"
@@ -824,3 +826,220 @@ const VMStateDescription vmstate_pcie_aer_log = {
}
};
+void pcie_aer_inject_error_print(Monitor *mon, const QObject *data)
+{
+ QDict *qdict;
+ int devfn;
+ assert(qobject_type(data) == QTYPE_QDICT);
+ qdict = qobject_to_qdict(data);
+
+ devfn = (int)qdict_get_int(qdict, "devfn");
+ monitor_printf(mon, "OK domain: %x, bus: %x devfn: %x.%x\n",
+ (int) qdict_get_int(qdict, "domain"),
+ (int) qdict_get_int(qdict, "bus"),
+ PCI_SLOT(devfn), PCI_FUNC(devfn));
+}
+
+typedef struct PCIEAERErrorName {
+ const char *name;
+ uint32_t val;
+ bool correctable;
+} PCIEAERErrorName;
+
+/*
+ * AER error name -> value convertion table
+ * This naming scheme is same to linux aer-injection tool.
+ */
+static const struct PCIEAERErrorName pcie_aer_error_list[] = {
+ {
+ .name = "TRAIN",
+ .val = PCI_ERR_UNC_TRAIN,
+ .correctable = false,
+ }, {
+ .name = "DLP",
+ .val = PCI_ERR_UNC_DLP,
+ .correctable = false,
+ }, {
+ .name = "SDN",
+ .val = PCI_ERR_UNC_SDN,
+ .correctable = false,
+ }, {
+ .name = "POISON_TLP",
+ .val = PCI_ERR_UNC_POISON_TLP,
+ .correctable = false,
+ }, {
+ .name = "FCP",
+ .val = PCI_ERR_UNC_FCP,
+ .correctable = false,
+ }, {
+ .name = "COMP_TIME",
+ .val = PCI_ERR_UNC_COMP_TIME,
+ .correctable = false,
+ }, {
+ .name = "COMP_ABORT",
+ .val = PCI_ERR_UNC_COMP_ABORT,
+ .correctable = false,
+ }, {
+ .name = "UNX_COMP",
+ .val = PCI_ERR_UNC_UNX_COMP,
+ .correctable = false,
+ }, {
+ .name = "RX_OVER",
+ .val = PCI_ERR_UNC_RX_OVER,
+ .correctable = false,
+ }, {
+ .name = "MALF_TLP",
+ .val = PCI_ERR_UNC_MALF_TLP,
+ .correctable = false,
+ }, {
+ .name = "ECRC",
+ .val = PCI_ERR_UNC_ECRC,
+ .correctable = false,
+ }, {
+ .name = "UNSUP",
+ .val = PCI_ERR_UNC_UNSUP,
+ .correctable = false,
+ }, {
+ .name = "ACSV",
+ .val = PCI_ERR_UNC_ACSV,
+ .correctable = false,
+ }, {
+ .name = "INTN",
+ .val = PCI_ERR_UNC_INTN,
+ .correctable = false,
+ }, {
+ .name = "MCBTLP",
+ .val = PCI_ERR_UNC_MCBTLP,
+ .correctable = false,
+ }, {
+ .name = "ATOP_EBLOCKED",
+ .val = PCI_ERR_UNC_ATOP_EBLOCKED,
+ .correctable = false,
+ }, {
+ .name = "TLP_PRF_BLOCKED",
+ .val = PCI_ERR_UNC_TLP_PRF_BLOCKED,
+ .correctable = false,
+ }, {
+ .name = "RCVR",
+ .val = PCI_ERR_COR_RCVR,
+ .correctable = true,
+ }, {
+ .name = "BAD_TLP",
+ .val = PCI_ERR_COR_BAD_TLP,
+ .correctable = true,
+ }, {
+ .name = "BAD_DLLP",
+ .val = PCI_ERR_COR_BAD_DLLP,
+ .correctable = true,
+ }, {
+ .name = "REP_ROLL",
+ .val = PCI_ERR_COR_REP_ROLL,
+ .correctable = true,
+ }, {
+ .name = "REP_TIMER",
+ .val = PCI_ERR_COR_REP_TIMER,
+ .correctable = true,
+ }, {
+ .name = "ADV_NONFATAL",
+ .val = PCI_ERR_COR_ADV_NONFATAL,
+ .correctable = true,
+ }, {
+ .name = "INTERNAL",
+ .val = PCI_ERR_COR_INTERNAL,
+ .correctable = true,
+ }, {
+ .name = "HL_OVERFLOW",
+ .val = PCI_ERR_COR_HL_OVERFLOW,
+ .correctable = true,
+ },
+};
+
+static int pcie_aer_parse_error_string(const char *error_name,
+ uint32_t *status, bool *correctable)
+{
+ int i;
+
+ for (i = 0; i < ARRAY_SIZE(pcie_aer_error_list); i++) {
+ const PCIEAERErrorName *e = &pcie_aer_error_list[i];
+ if (strcmp(error_name, e->name)) {
+ continue;
+ }
+
+ *status = e->val;
+ *correctable = e->correctable;
+ return 0;
+ }
+ return -1;
+}
+
+int do_pcie_aer_inejct_error(Monitor *mon,
+ const QDict *qdict, QObject **ret_data)
+{
+ const char *pci_dev_path = qdict_get_str(qdict, "pci_dev_path");
+ const char *error_name;
+ uint32_t error_status;
+ bool correctable;
+ PCIDevice *dev;
+ PCIEAERErr err;
+ int ret;
+
+ if (pci_parse_dev_path(pci_dev_path, &dev)) {
+ monitor_printf(mon,
+ "pci device path is invalid or device not found. %s\n",
+ pci_dev_path);
+ }
+ if (!pci_is_express(dev)) {
+ monitor_printf(mon, "the device doesn't support pci express. %s\n",
+ pci_dev_path);
+ return -1;
+ }
+
+ error_name = qdict_get_str(qdict, "error_status");
+ if (pcie_aer_parse_error_string(error_name, &error_status, &correctable)) {
+ char *e = NULL;
+ error_status = strtoul(error_name, &e, 0);
+ correctable = !!qdict_get_int(qdict, "correctable");
+ if (!e || *e != '\0') {
+ monitor_printf(mon, "invalid error status value. \"%s\"",
+ error_name);
+ return -1;
+ }
+ }
+ err.source_id = (pci_bus_num(dev->bus) << 8) | dev->devfn;
+
+ err.flags = 0;
+ if (correctable) {
+ err.flags |= PCIE_AER_ERR_IS_CORRECTABLE;
+ }
+ if (qdict_get_int(qdict, "advisory_non_fatal")) {
+ err.flags |= PCIE_AER_ERR_MAYBE_ADVISORY;
+ }
+ if (qdict_haskey(qdict, "header0")) {
+ err.flags |= PCIE_AER_ERR_HEADER_VALID;
+ }
+ if (qdict_haskey(qdict, "prefix0")) {
+ err.flags |= PCIE_AER_ERR_TLP_PREFIX_PRESENT;
+ }
+
+ err.header[0] = qdict_get_try_int(qdict, "header0", 0);
+ err.header[1] = qdict_get_try_int(qdict, "header1", 0);
+ err.header[2] = qdict_get_try_int(qdict, "header2", 0);
+ err.header[3] = qdict_get_try_int(qdict, "header3", 0);
+
+ err.prefix[0] = qdict_get_try_int(qdict, "prefix0", 0);
+ err.prefix[1] = qdict_get_try_int(qdict, "prefix1", 0);
+ err.prefix[2] = qdict_get_try_int(qdict, "prefix2", 0);
+ err.prefix[3] = qdict_get_try_int(qdict, "prefix3", 0);
+
+ ret = pcie_aer_inject_error(dev, &err);
+ *ret_data = qobject_from_jsonf("{'dev_path': %s, "
+ "'domain': %d, 'bus': %d, 'devfn': %d, "
+ "'ret': %d}",
+ pci_dev_path,
+ pci_find_domain(dev->bus),
+ pci_bus_num(dev->bus), dev->devfn,
+ ret);
+ assert(*ret_data);
+
+ return 0;
+}
diff --git a/sysemu.h b/sysemu.h
index b81a70e..99c7909 100644
--- a/sysemu.h
+++ b/sysemu.h
@@ -151,6 +151,11 @@ void pci_device_hot_add(Monitor *mon, const QDict *qdict);
void drive_hot_add(Monitor *mon, const QDict *qdict);
void do_pci_device_hot_remove(Monitor *mon, const QDict *qdict);
+/* pcie aer error injection */
+void pcie_aer_inject_error_print(Monitor *mon, const QObject *data);
+int do_pcie_aer_inejct_error(Monitor *mon,
+ const QDict *qdict, QObject **ret_data);
+
/* serial ports */
#define MAX_SERIAL_PORTS 4
--
1.7.1.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [Qemu-devel] [PATCH v8 09/11] ioh3420: support aer
2010-11-15 7:30 [Qemu-devel] [PATCH v8 00/11] pcie port switch emulators Isaku Yamahata
` (7 preceding siblings ...)
2010-11-15 7:30 ` [Qemu-devel] [PATCH v8 08/11] pcie/aer: glue aer error injection into qemu monitor Isaku Yamahata
@ 2010-11-15 7:30 ` Isaku Yamahata
2010-11-15 7:30 ` [Qemu-devel] [PATCH v8 10/11] x3130/upstream: " Isaku Yamahata
2010-11-15 7:30 ` [Qemu-devel] [PATCH v8 11/11] x3130/downstream: " Isaku Yamahata
10 siblings, 0 replies; 16+ messages in thread
From: Isaku Yamahata @ 2010-11-15 7:30 UTC (permalink / raw)
To: qemu-devel; +Cc: skandasa, adnan, wexu2, mst, yamahata, etmartin
Add aer support.
Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>
---
hw/ioh3420.c | 51 +++++++++++++++++++++++++++++++++++++++++++++------
1 files changed, 45 insertions(+), 6 deletions(-)
diff --git a/hw/ioh3420.c b/hw/ioh3420.c
index 3cc129f..4eecf2f 100644
--- a/hw/ioh3420.c
+++ b/hw/ioh3420.c
@@ -36,25 +36,59 @@
#define IOH_EP_EXP_OFFSET 0x90
#define IOH_EP_AER_OFFSET 0x100
+/*
+ * If two MSI vector are allocated, Advanced Error Interrupt Message Number
+ * is 1. otherwise 0.
+ * 17.12.5.10 RPERRSTS, 32:27 bit Advanced Error Interrupt Message Number.
+ */
+static uint8_t ioh3420_aer_vector(const PCIDevice *d)
+{
+ switch (msi_nr_vectors_allocated(d)) {
+ case 1:
+ return 0;
+ case 2:
+ return 1;
+ case 4:
+ case 8:
+ case 16:
+ case 32:
+ default:
+ break;
+ }
+ abort();
+ return 0;
+}
+
+static void ioh3420_aer_vector_update(PCIDevice *d)
+{
+ pcie_aer_root_set_vector(d, ioh3420_aer_vector(d));
+}
+
static void ioh3420_write_config(PCIDevice *d,
uint32_t address, uint32_t val, int len)
{
+ uint32_t root_cmd =
+ pci_get_long(d->config + d->exp.aer_cap + PCI_ERR_ROOT_COMMAND);
+
pci_bridge_write_config(d, address, val, len);
msi_write_config(d, address, val, len);
+ ioh3420_aer_vector_update(d);
pcie_cap_slot_write_config(d, address, val, len);
- /* TODO: AER */
+ pcie_aer_write_config(d, address, val, len);
+ pcie_aer_root_write_config(d, address, val, len, root_cmd);
}
static void ioh3420_reset(DeviceState *qdev)
{
PCIDevice *d = DO_UPCAST(PCIDevice, qdev, qdev);
msi_reset(d);
+ ioh3420_aer_vector_update(d);
pcie_cap_root_reset(d);
pcie_cap_deverr_reset(d);
pcie_cap_slot_reset(d);
+ pcie_aer_root_reset(d);
pci_bridge_reset(qdev);
pci_bridge_disable_base_limit(d);
- /* TODO: AER */
}
static int ioh3420_initfn(PCIDevice *d)
@@ -98,13 +132,15 @@ static int ioh3420_initfn(PCIDevice *d)
return rc;
}
pcie_cap_root_init(d);
- /* TODO: AER */
+ pcie_aer_init(d, IOH_EP_AER_OFFSET);
+ pcie_aer_root_init(d);
+ ioh3420_aer_vector_update(d);
return 0;
}
static int ioh3420_exitfn(PCIDevice *d)
{
- /* TODO: AER */
+ pcie_aer_exit(d);
msi_uninit(d);
pcie_cap_exit(d);
return pci_bridge_exitfn(d);
@@ -142,7 +178,8 @@ static const VMStateDescription vmstate_ioh3420 = {
.post_load = pcie_cap_slot_post_load,
.fields = (VMStateField[]) {
VMSTATE_PCIE_DEVICE(port.br.dev, PCIESlot),
- /* TODO: AER */
+ VMSTATE_STRUCT(port.br.dev.exp.aer_log, PCIESlot, 0,
+ vmstate_pcie_aer_log, PCIEAERLog),
VMSTATE_END_OF_LIST()
}
};
@@ -164,7 +201,9 @@ static PCIDeviceInfo ioh3420_info = {
DEFINE_PROP_UINT8("port", PCIESlot, port.port, 0),
DEFINE_PROP_UINT8("chassis", PCIESlot, chassis, 0),
DEFINE_PROP_UINT16("slot", PCIESlot, slot, 0),
- /* TODO: AER */
+ DEFINE_PROP_UINT16("aer_log_max", PCIESlot,
+ port.br.dev.exp.aer_log.log_max,
+ PCIE_AER_LOG_MAX_DEFAULT),
DEFINE_PROP_END_OF_LIST(),
}
};
--
1.7.1.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [Qemu-devel] [PATCH v8 10/11] x3130/upstream: support aer
2010-11-15 7:30 [Qemu-devel] [PATCH v8 00/11] pcie port switch emulators Isaku Yamahata
` (8 preceding siblings ...)
2010-11-15 7:30 ` [Qemu-devel] [PATCH v8 09/11] ioh3420: support aer Isaku Yamahata
@ 2010-11-15 7:30 ` Isaku Yamahata
2010-11-15 7:30 ` [Qemu-devel] [PATCH v8 11/11] x3130/downstream: " Isaku Yamahata
10 siblings, 0 replies; 16+ messages in thread
From: Isaku Yamahata @ 2010-11-15 7:30 UTC (permalink / raw)
To: qemu-devel; +Cc: skandasa, adnan, wexu2, mst, yamahata, etmartin
add aer support.
Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>
---
hw/xio3130_upstream.c | 12 +++++++-----
1 files changed, 7 insertions(+), 5 deletions(-)
diff --git a/hw/xio3130_upstream.c b/hw/xio3130_upstream.c
index d9d637f..29bc814 100644
--- a/hw/xio3130_upstream.c
+++ b/hw/xio3130_upstream.c
@@ -41,7 +41,7 @@ static void xio3130_upstream_write_config(PCIDevice *d, uint32_t address,
pci_bridge_write_config(d, address, val, len);
pcie_cap_flr_write_config(d, address, val, len);
msi_write_config(d, address, val, len);
- /* TODO: AER */
+ pcie_aer_write_config(d, address, val, len);
}
static void xio3130_upstream_reset(DeviceState *qdev)
@@ -89,14 +89,14 @@ static int xio3130_upstream_initfn(PCIDevice *d)
pcie_cap_flr_init(d);
pcie_cap_deverr_init(d);
- /* TODO: AER */
+ pcie_aer_init(d, XIO3130_AER_OFFSET);
return 0;
}
static int xio3130_upstream_exitfn(PCIDevice *d)
{
- /* TODO: AER */
+ pcie_aer_exit(d);
msi_uninit(d);
pcie_cap_exit(d);
return pci_bridge_exitfn(d);
@@ -131,7 +131,8 @@ static const VMStateDescription vmstate_xio3130_upstream = {
.minimum_version_id_old = 1,
.fields = (VMStateField[]) {
VMSTATE_PCIE_DEVICE(br.dev, PCIEPort),
- /* TODO: AER */
+ VMSTATE_STRUCT(br.dev.exp.aer_log, PCIEPort, 0, vmstate_pcie_aer_log,
+ PCIEAERLog),
VMSTATE_END_OF_LIST()
}
};
@@ -151,7 +152,8 @@ static PCIDeviceInfo xio3130_upstream_info = {
.qdev.props = (Property[]) {
DEFINE_PROP_UINT8("port", PCIEPort, port, 0),
- /* TODO: AER */
+ DEFINE_PROP_UINT16("aer_log_max", PCIEPort, br.dev.exp.aer_log.log_max,
+ PCIE_AER_LOG_MAX_DEFAULT),
DEFINE_PROP_END_OF_LIST(),
}
};
--
1.7.1.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [Qemu-devel] [PATCH v8 11/11] x3130/downstream: support aer.
2010-11-15 7:30 [Qemu-devel] [PATCH v8 00/11] pcie port switch emulators Isaku Yamahata
` (9 preceding siblings ...)
2010-11-15 7:30 ` [Qemu-devel] [PATCH v8 10/11] x3130/upstream: " Isaku Yamahata
@ 2010-11-15 7:30 ` Isaku Yamahata
10 siblings, 0 replies; 16+ messages in thread
From: Isaku Yamahata @ 2010-11-15 7:30 UTC (permalink / raw)
To: qemu-devel; +Cc: skandasa, adnan, wexu2, mst, yamahata, etmartin
add aer support.
Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>
---
hw/xio3130_downstream.c | 13 ++++++++-----
1 files changed, 8 insertions(+), 5 deletions(-)
diff --git a/hw/xio3130_downstream.c b/hw/xio3130_downstream.c
index 854eba8..f90415f 100644
--- a/hw/xio3130_downstream.c
+++ b/hw/xio3130_downstream.c
@@ -42,7 +42,7 @@ static void xio3130_downstream_write_config(PCIDevice *d, uint32_t address,
pcie_cap_flr_write_config(d, address, val, len);
pcie_cap_slot_write_config(d, address, val, len);
msi_write_config(d, address, val, len);
- /* TODO: AER */
+ pcie_aer_write_config(d, address, val, len);
}
static void xio3130_downstream_reset(DeviceState *qdev)
@@ -97,14 +97,14 @@ static int xio3130_downstream_initfn(PCIDevice *d)
return rc;
}
pcie_cap_ari_init(d);
- /* TODO: AER */
+ pcie_aer_init(d, XIO3130_AER_OFFSET);
return 0;
}
static int xio3130_downstream_exitfn(PCIDevice *d)
{
- /* TODO: AER */
+ pcie_aer_exit(d);
msi_uninit(d);
pcie_cap_exit(d);
return pci_bridge_exitfn(d);
@@ -144,7 +144,8 @@ static const VMStateDescription vmstate_xio3130_downstream = {
.post_load = pcie_cap_slot_post_load,
.fields = (VMStateField[]) {
VMSTATE_PCIE_DEVICE(port.br.dev, PCIESlot),
- /* TODO: AER */
+ VMSTATE_STRUCT(port.br.dev.exp.aer_log, PCIESlot, 0,
+ vmstate_pcie_aer_log, PCIEAERLog),
VMSTATE_END_OF_LIST()
}
};
@@ -166,7 +167,9 @@ static PCIDeviceInfo xio3130_downstream_info = {
DEFINE_PROP_UINT8("port", PCIESlot, port.port, 0),
DEFINE_PROP_UINT8("chassis", PCIESlot, chassis, 0),
DEFINE_PROP_UINT16("slot", PCIESlot, slot, 0),
- /* TODO: AER */
+ DEFINE_PROP_UINT16("aer_log_max", PCIESlot,
+ port.br.dev.exp.aer_log.log_max,
+ PCIE_AER_LOG_MAX_DEFAULT),
DEFINE_PROP_END_OF_LIST(),
}
};
--
1.7.1.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [Qemu-devel] Re: [PATCH v8 07/11] pci: introduce a parser for pci device path
2010-11-15 7:30 ` [Qemu-devel] [PATCH v8 07/11] pci: introduce a parser for pci device path Isaku Yamahata
@ 2010-11-15 8:06 ` Michael S. Tsirkin
2010-11-15 8:57 ` Isaku Yamahata
0 siblings, 1 reply; 16+ messages in thread
From: Michael S. Tsirkin @ 2010-11-15 8:06 UTC (permalink / raw)
To: Isaku Yamahata; +Cc: skandasa, adnan, wexu2, gleb, qemu-devel, etmartin
On Mon, Nov 15, 2010 at 04:30:43PM +0900, Isaku Yamahata wrote:
> introduce a function to parse pci device path of
> the format, [Domain:]Slot.Function:Slot.Function....:Slot.Function.
>
> Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>
Hmm.
How about we use openfirmware path like what Gleb's patch does,
with a fallback to bus:dev.fn for when it's unambiguous?
> ---
> hw/pci.c | 87 ++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++++
> hw/pci.h | 1 +
> 2 files changed, 88 insertions(+), 0 deletions(-)
>
> diff --git a/hw/pci.c b/hw/pci.c
> index fba765b..6a9a5ef 100644
> --- a/hw/pci.c
> +++ b/hw/pci.c
> @@ -433,6 +433,93 @@ static void pci_set_default_subsystem_id(PCIDevice *pci_dev)
> }
>
> /*
> + * Parse format [Domain:]Slot.Function:Slot.Function....:Slot.Function
> + * and get PCIDevice
> + * return 0 on success
> + * -1 on error: format is invalid or device isn't found.
> + */
> +int pci_parse_dev_path(const char *addr, PCIDevice **pdev)
> +{
> + unsigned long domain;
> + unsigned long slot;
> + unsigned long func;
> + const char *p;
> + char *e;
> + unsigned long val;
> + PCIBus *bus;
> + PCIBus *child_bus;
> + PCIDevice *d;
> +
> + p = addr;
> + val = strtoul(p, &e, 0);
> + if (e == p) {
> + return -1;
> + }
> + if (*e == ':') {
> + domain = val;
> + p = e + 1;
> + val = strtoul(p, &e, 0);
> + if (e == p) {
> + return -1;
> + }
> + } else if (*e == '.'){
> + domain = 0;
> + } else {
> + return -1;
> + }
> + if (domain > 0xffff) {
> + return -1;
> + }
> +
> + bus = pci_find_root_bus(domain);
> + if (!bus) {
> + return -1;
> + }
> +
> + for (;;) {
> + slot = val;
> + if (*e != '.') {
> + return -1;
> + }
> + p = e + 1;
> + val = strtoul(p, &e, 0);
> + if (e == p) {
> + return -1;
> + }
> + func = val;
> + if (slot > 0x1f || func >= PCI_FUNC_MAX) {
> + return -1;
> + }
> + d = bus->devices[PCI_DEVFN(slot, func)];
> + if (!d) {
> + return -1;
> + }
> + if (*e == '\0') {
> + break;
> + }
> +
> + if (*e != ':') {
> + return -1;
> + }
> + p = e + 1;
> + val = strtoul(p, &e, 0);
> + if (e == p) {
> + return -1;
> + }
> + QLIST_FOREACH(child_bus, &bus->child, sibling) {
> + if (child_bus->parent_dev == d) {
> + bus = child_bus;
> + continue;
> + }
> + }
> + return -1;
> + }
> +
> + *pdev = d;
> + return 0;
> +}
> +
> +/*
> * Parse [[<domain>:]<bus>:]<slot>, return -1 on error if funcp == NULL
> * [[<domain>:]<bus>:]<slot>.<func>, return -1 on error
> */
> diff --git a/hw/pci.h b/hw/pci.h
> index 7100804..8c16f91 100644
> --- a/hw/pci.h
> +++ b/hw/pci.h
> @@ -239,6 +239,7 @@ PCIBus *pci_find_bus(PCIBus *bus, int bus_num);
> PCIDevice *pci_find_device(PCIBus *bus, int bus_num, int slot, int function);
> PCIBus *pci_get_bus_devfn(int *devfnp, const char *devaddr);
>
> +int pci_parse_dev_path(const char *addr, PCIDevice **pdev);
> int pci_parse_devaddr(const char *addr, int *domp, int *busp,
> unsigned int *slotp, unsigned int *funcp);
> int pci_read_devaddr(Monitor *mon, const char *addr, int *domp, int *busp,
> --
> 1.7.1.1
^ permalink raw reply [flat|nested] 16+ messages in thread
* [Qemu-devel] Re: [PATCH v8 01/11] pci: revise pci command register initialization
2010-11-15 7:30 ` [Qemu-devel] [PATCH v8 01/11] pci: revise pci command register initialization Isaku Yamahata
@ 2010-11-15 8:09 ` Michael S. Tsirkin
0 siblings, 0 replies; 16+ messages in thread
From: Michael S. Tsirkin @ 2010-11-15 8:09 UTC (permalink / raw)
To: Isaku Yamahata; +Cc: skandasa, adnan, etmartin, qemu-devel, wexu2
On Mon, Nov 15, 2010 at 04:30:37PM +0900, Isaku Yamahata wrote:
> This patch cleans up command register initialization with
> comments.
>
> Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>
Probably just fold with the next patch.
> ---
> hw/pci.c | 42 ++++++++++++++++++++++++++++++++++++++++++
> 1 files changed, 42 insertions(+), 0 deletions(-)
>
> diff --git a/hw/pci.c b/hw/pci.c
> index 962886e..b70a568 100644
> --- a/hw/pci.c
> +++ b/hw/pci.c
> @@ -544,8 +544,50 @@ static void pci_init_wmask(PCIDevice *dev)
>
> dev->wmask[PCI_CACHE_LINE_SIZE] = 0xff;
> dev->wmask[PCI_INTERRUPT_LINE] = 0xff;
> +
> + /*
> + * bit 0: PCI_COMMAND_IO
> + * type 0: if IO BAR is used, RW
> + * type 1: RW
> + * bit 1: PCI_COMMAND_MEMORY
> + * type 0: if IO BAR is used, RW
> + * type 1: RW
> + * bit 2: PCI_COMMAND_MASTER
> + * type 0: RW if bus master
> + * type 1: RW
> + * bit 3: PCI_COMMAND_SPECIAL
> + * RO=0, optionally RW: Such device should set this bit itself
> + * bit 4: PCI_COMMAND_INVALIDATE
> + * RO=0, optionally RW: Such device should set this bit itself
> + * bit 5: PCI_COMMAND_VGA_PALETTE
> + * RO=0, optionally RW: Such device should set this bit itself
> + * bit 6: PCI_COMMAND_PARITY
> + * RW with exceptions: Such device should clear this bit itself
> + * Given that qemu doesn't emulate pci bus cycles, so that there
> + * is no place to generate parity error. So just making this
> + * register RW is okay because there is no place which refers
> + * this bit.
> + * TODO: When device assignment tried to inject PERR# into qemu,
> + * some extra work would be needed.
> + * bit 7: PCI_COMMAND_WAIT: reserved (PCI 3.0)
> + * RO=0
> + * bit 8: PCI_COMMAND_SERR
> + * RW with exceptions: Such device should clear this bit itself
> + * Given that qemu doesn't emulate pci bus cycles, so that there
> + * is no place to generate system error. So just making this
> + * register RW is okay because there is no place which refers
> + * this bit.
> + * TODO: When device assignment tried to inject SERR# into qemu,
> + * some extra work would be needed.
> + * bit 9: PCI_COMMAND_FAST_BACK
> + * RO=0, optionally RW: Such device should set this bit itself
> + * bit 10: PCI_COMMAND_INTX_DISABLE
> + * RW
> + * bit 11-15: reserved
> + */
> pci_set_word(dev->wmask + PCI_COMMAND,
> PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER |
> + PCI_COMMAND_PARITY | PCI_COMMAND_SERR |
> PCI_COMMAND_INTX_DISABLE);
>
> memset(dev->wmask + PCI_CONFIG_HEADER_SIZE, 0xff,
> --
> 1.7.1.1
^ permalink raw reply [flat|nested] 16+ messages in thread
* [Qemu-devel] Re: [PATCH v8 07/11] pci: introduce a parser for pci device path
2010-11-15 8:06 ` [Qemu-devel] " Michael S. Tsirkin
@ 2010-11-15 8:57 ` Isaku Yamahata
2010-11-15 9:03 ` Gleb Natapov
0 siblings, 1 reply; 16+ messages in thread
From: Isaku Yamahata @ 2010-11-15 8:57 UTC (permalink / raw)
To: Michael S. Tsirkin; +Cc: skandasa, adnan, wexu2, gleb, qemu-devel, etmartin
On Mon, Nov 15, 2010 at 10:06:13AM +0200, Michael S. Tsirkin wrote:
> On Mon, Nov 15, 2010 at 04:30:43PM +0900, Isaku Yamahata wrote:
> > introduce a function to parse pci device path of
> > the format, [Domain:]Slot.Function:Slot.Function....:Slot.Function.
> >
> > Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>
>
> Hmm.
> How about we use openfirmware path like what Gleb's patch does,
> with a fallback to bus:dev.fn for when it's unambiguous?
Okay, let me check my understanding of the format.
The openfirmware path in pci case looks like
/pci@<ioport>/<device name>@<slot>,<func>/.../<device name>@<slot>,<func>
"pci@<ioport>" corresponds to pci domain. So <mmio address> should be
also supported in addition to <ioport>.
Maybe we'd like "<device name>@" to be optional.
So the parser would accept something like
/{<ioport>, <mmio addr>}/<slot>,<func>/.../<slot>,<func>
--
yamahata
^ permalink raw reply [flat|nested] 16+ messages in thread
* [Qemu-devel] Re: [PATCH v8 07/11] pci: introduce a parser for pci device path
2010-11-15 8:57 ` Isaku Yamahata
@ 2010-11-15 9:03 ` Gleb Natapov
0 siblings, 0 replies; 16+ messages in thread
From: Gleb Natapov @ 2010-11-15 9:03 UTC (permalink / raw)
To: Isaku Yamahata
Cc: skandasa, adnan, wexu2, Michael S. Tsirkin, qemu-devel, etmartin
On Mon, Nov 15, 2010 at 05:57:40PM +0900, Isaku Yamahata wrote:
> On Mon, Nov 15, 2010 at 10:06:13AM +0200, Michael S. Tsirkin wrote:
> > On Mon, Nov 15, 2010 at 04:30:43PM +0900, Isaku Yamahata wrote:
> > > introduce a function to parse pci device path of
> > > the format, [Domain:]Slot.Function:Slot.Function....:Slot.Function.
> > >
> > > Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>
> >
> > Hmm.
> > How about we use openfirmware path like what Gleb's patch does,
> > with a fallback to bus:dev.fn for when it's unambiguous?
>
> Okay, let me check my understanding of the format.
>
> The openfirmware path in pci case looks like
> /pci@<ioport>/<device name>@<slot>,<func>/.../<device name>@<slot>,<func>
>
> "pci@<ioport>" corresponds to pci domain. So <mmio address> should be
> also supported in addition to <ioport>.
>
Correct.
> Maybe we'd like "<device name>@" to be optional.
> So the parser would accept something like
> /{<ioport>, <mmio addr>}/<slot>,<func>/.../<slot>,<func>
My patch series has pci_dev_fw_name() function that fills in <device name>
for you, so no reason to make it optional. If you still want to make it
optional @ should stay, so it should be /@ioport/@slot.func/
--
Gleb.
^ permalink raw reply [flat|nested] 16+ messages in thread
end of thread, other threads:[~2010-11-15 9:04 UTC | newest]
Thread overview: 16+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2010-11-15 7:30 [Qemu-devel] [PATCH v8 00/11] pcie port switch emulators Isaku Yamahata
2010-11-15 7:30 ` [Qemu-devel] [PATCH v8 01/11] pci: revise pci command register initialization Isaku Yamahata
2010-11-15 8:09 ` [Qemu-devel] " Michael S. Tsirkin
2010-11-15 7:30 ` [Qemu-devel] [PATCH v8 02/11] pci: clean up pci command register io/memory bit initialization Isaku Yamahata
2010-11-15 7:30 ` [Qemu-devel] [PATCH v8 03/11] pci: fix accesses to pci status register Isaku Yamahata
2010-11-15 7:30 ` [Qemu-devel] [PATCH v8 04/11] pci: clean up of " Isaku Yamahata
2010-11-15 7:30 ` [Qemu-devel] [PATCH v8 05/11] pcie_regs.h: more constants Isaku Yamahata
2010-11-15 7:30 ` [Qemu-devel] [PATCH v8 06/11] pcie/aer: helper functions for pcie aer capability Isaku Yamahata
2010-11-15 7:30 ` [Qemu-devel] [PATCH v8 07/11] pci: introduce a parser for pci device path Isaku Yamahata
2010-11-15 8:06 ` [Qemu-devel] " Michael S. Tsirkin
2010-11-15 8:57 ` Isaku Yamahata
2010-11-15 9:03 ` Gleb Natapov
2010-11-15 7:30 ` [Qemu-devel] [PATCH v8 08/11] pcie/aer: glue aer error injection into qemu monitor Isaku Yamahata
2010-11-15 7:30 ` [Qemu-devel] [PATCH v8 09/11] ioh3420: support aer Isaku Yamahata
2010-11-15 7:30 ` [Qemu-devel] [PATCH v8 10/11] x3130/upstream: " Isaku Yamahata
2010-11-15 7:30 ` [Qemu-devel] [PATCH v8 11/11] x3130/downstream: " Isaku Yamahata
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