From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from [140.186.70.92] (port=41185 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1PHu8k-0007vX-1B for qemu-devel@nongnu.org; Mon, 15 Nov 2010 03:10:16 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1PHu8f-00016z-Q6 for qemu-devel@nongnu.org; Mon, 15 Nov 2010 03:10:13 -0500 Received: from mx1.redhat.com ([209.132.183.28]:3490) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1PHu8f-00016r-FA for qemu-devel@nongnu.org; Mon, 15 Nov 2010 03:10:09 -0500 Date: Mon, 15 Nov 2010 10:09:56 +0200 From: "Michael S. Tsirkin" Message-ID: <20101115080956.GF22248@redhat.com> References: <7e4c6573d912e9a45c8515b86c39c348002aa701.1289805831.git.yamahata@valinux.co.jp> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <7e4c6573d912e9a45c8515b86c39c348002aa701.1289805831.git.yamahata@valinux.co.jp> Subject: [Qemu-devel] Re: [PATCH v8 01/11] pci: revise pci command register initialization List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Isaku Yamahata Cc: skandasa@cisco.com, adnan@khaleel.us, etmartin@cisco.com, qemu-devel@nongnu.org, wexu2@cisco.com On Mon, Nov 15, 2010 at 04:30:37PM +0900, Isaku Yamahata wrote: > This patch cleans up command register initialization with > comments. > > Signed-off-by: Isaku Yamahata Probably just fold with the next patch. > --- > hw/pci.c | 42 ++++++++++++++++++++++++++++++++++++++++++ > 1 files changed, 42 insertions(+), 0 deletions(-) > > diff --git a/hw/pci.c b/hw/pci.c > index 962886e..b70a568 100644 > --- a/hw/pci.c > +++ b/hw/pci.c > @@ -544,8 +544,50 @@ static void pci_init_wmask(PCIDevice *dev) > > dev->wmask[PCI_CACHE_LINE_SIZE] = 0xff; > dev->wmask[PCI_INTERRUPT_LINE] = 0xff; > + > + /* > + * bit 0: PCI_COMMAND_IO > + * type 0: if IO BAR is used, RW > + * type 1: RW > + * bit 1: PCI_COMMAND_MEMORY > + * type 0: if IO BAR is used, RW > + * type 1: RW > + * bit 2: PCI_COMMAND_MASTER > + * type 0: RW if bus master > + * type 1: RW > + * bit 3: PCI_COMMAND_SPECIAL > + * RO=0, optionally RW: Such device should set this bit itself > + * bit 4: PCI_COMMAND_INVALIDATE > + * RO=0, optionally RW: Such device should set this bit itself > + * bit 5: PCI_COMMAND_VGA_PALETTE > + * RO=0, optionally RW: Such device should set this bit itself > + * bit 6: PCI_COMMAND_PARITY > + * RW with exceptions: Such device should clear this bit itself > + * Given that qemu doesn't emulate pci bus cycles, so that there > + * is no place to generate parity error. So just making this > + * register RW is okay because there is no place which refers > + * this bit. > + * TODO: When device assignment tried to inject PERR# into qemu, > + * some extra work would be needed. > + * bit 7: PCI_COMMAND_WAIT: reserved (PCI 3.0) > + * RO=0 > + * bit 8: PCI_COMMAND_SERR > + * RW with exceptions: Such device should clear this bit itself > + * Given that qemu doesn't emulate pci bus cycles, so that there > + * is no place to generate system error. So just making this > + * register RW is okay because there is no place which refers > + * this bit. > + * TODO: When device assignment tried to inject SERR# into qemu, > + * some extra work would be needed. > + * bit 9: PCI_COMMAND_FAST_BACK > + * RO=0, optionally RW: Such device should set this bit itself > + * bit 10: PCI_COMMAND_INTX_DISABLE > + * RW > + * bit 11-15: reserved > + */ > pci_set_word(dev->wmask + PCI_COMMAND, > PCI_COMMAND_IO | PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER | > + PCI_COMMAND_PARITY | PCI_COMMAND_SERR | > PCI_COMMAND_INTX_DISABLE); > > memset(dev->wmask + PCI_CONFIG_HEADER_SIZE, 0xff, > -- > 1.7.1.1