From mboxrd@z Thu Jan  1 00:00:00 1970
Received: from [140.186.70.92] (port=60936 helo=eggs.gnu.org)
	by lists.gnu.org with esmtp (Exim 4.43) id 1PN7r5-0005LN-Ft
	for qemu-devel@nongnu.org; Mon, 29 Nov 2010 12:49:36 -0500
Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71)
	(envelope-from <froydnj@codesourcery.com>) id 1PN7r0-000248-V5
	for qemu-devel@nongnu.org; Mon, 29 Nov 2010 12:49:35 -0500
Received: from mail.codesourcery.com ([38.113.113.100]:45052)
	by eggs.gnu.org with esmtp (Exim 4.71)
	(envelope-from <froydnj@codesourcery.com>) id 1PN7r0-00023n-Ld
	for qemu-devel@nongnu.org; Mon, 29 Nov 2010 12:49:30 -0500
Date: Mon, 29 Nov 2010 09:49:28 -0800
From: Nathan Froyd <froydnj@codesourcery.com>
Subject: Re: [Qemu-devel] [PATCH 08/12] ARM: Return correct result for
	single<->double conversion of NaN
Message-ID: <20101129174928.GE8544@codesourcery.com>
References: <1290538431-13170-1-git-send-email-peter.maydell@linaro.org>
	<1290538431-13170-9-git-send-email-peter.maydell@linaro.org>
MIME-Version: 1.0
Content-Type: text/plain; charset=us-ascii
Content-Disposition: inline
In-Reply-To: <1290538431-13170-9-git-send-email-peter.maydell@linaro.org>
List-Id: qemu-devel.nongnu.org
List-Unsubscribe: <http://lists.nongnu.org/mailman/listinfo/qemu-devel>,
	<mailto:qemu-devel-request@nongnu.org?subject=unsubscribe>
List-Archive: <http://lists.nongnu.org/archive/html/qemu-devel>
List-Post: <mailto:qemu-devel@nongnu.org>
List-Help: <mailto:qemu-devel-request@nongnu.org?subject=help>
List-Subscribe: <http://lists.nongnu.org/mailman/listinfo/qemu-devel>,
	<mailto:qemu-devel-request@nongnu.org?subject=subscribe>
To: Peter Maydell <peter.maydell@linaro.org>
Cc: qemu-devel@nongnu.org

On Tue, Nov 23, 2010 at 06:53:47PM +0000, Peter Maydell wrote:
> The ARM ARM defines that if the input to a single<->double conversion
> is a NaN then the output is always forced to be a quiet NaN by setting
> the most significant bit of the fraction part.
> 
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
> 
> @@ -2529,12 +2529,26 @@ float32 VFP_HELPER(tosiz, d)(float64 x, CPUState *env)
>  /* floating point conversion */
>  float64 VFP_HELPER(fcvtd, s)(float32 x, CPUState *env)
>  {
> -    return float32_to_float64(x, &env->vfp.fp_status);
> +    float64 r = float32_to_float64(x, &env->vfp.fp_status);
> +    /* ARM requires that S<->D conversion of any kind of NaN generates
> +     * a quiet NaN by forcing the most significant frac bit to 1.
> +     */
> +    if (float64_is_signaling_nan(r)) {
> +        return make_float64(float64_val(r) | (1LL << 51));
> +    }
> +    return r;
>  }

As with other NaN-handling patches, I don't think the bit-twiddling here
is a good idea.  Having a float*_maybe_silence_nan function in softfloat
would be a better approach.

-Nathan