Re: [Qemu-devel] [PATCH 2/6] [RFC] Emulation of GRLIB IRQMP as defined in GRLIB IP Core User's Manual.

["Edgar E. Iglesias" <edgar.iglesias@gmail.com>]

On Mon, Dec 06, 2010 at 10:26:03AM +0100, Fabien Chouteau wrote:
> 
> Signed-off-by: Fabien Chouteau <chouteau@adacore.com>
> ---
>  hw/grlib_irqmp.c |  416 ++++++++++++++++++++++++++++++++++++++++++++++++++++++
>  1 files changed, 416 insertions(+), 0 deletions(-)
> 
> diff --git a/hw/grlib_irqmp.c b/hw/grlib_irqmp.c
> new file mode 100644
> index 0000000..69e1553
> --- /dev/null
> +++ b/hw/grlib_irqmp.c
> @@ -0,0 +1,416 @@
> +/*
> + * QEMU GRLIB IRQMP Emulator
> + *
> + * (Multiprocessor and extended interrupt not supported)
> + *
> + * Copyright (c) 2010 AdaCore
> + *
> + * Permission is hereby granted, free of charge, to any person obtaining a copy
> + * of this software and associated documentation files (the "Software"), to deal
> + * in the Software without restriction, including without limitation the rights
> + * to use, copy, modify, merge, publish, distribute, sublicense, and/or sell
> + * copies of the Software, and to permit persons to whom the Software is
> + * furnished to do so, subject to the following conditions:
> + *
> + * The above copyright notice and this permission notice shall be included in
> + * all copies or substantial portions of the Software.
> + *
> + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
> + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
> + * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
> + * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
> + * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM,
> + * OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN
> + * THE SOFTWARE.
> + */
> +
> +#include "sysbus.h"
> +#include "cpu.h"
> +
> +#include "grlib.h"
> +
> +/* #define DEBUG_IRQ */
> +
> +#ifdef DEBUG_IRQ
> +#define DPRINTF(fmt, ...)                                       \
> +    do { printf("IRQMP: " fmt , ## __VA_ARGS__); } while (0)
> +#else
> +#define DPRINTF(fmt, ...)
> +#endif
> +
> +#define IRQMP_MAX_CPU 16
> +#define IRQMP_REG_SIZE 256      /* Size of memory mapped registers */
> +
> +/* Memory mapped register offsets */
> +#define LEVEL_OFFSET     0x00
> +#define PENDING_OFFSET   0x04
> +#define FORCE0_OFFSET    0x08
> +#define CLEAR_OFFSET     0x0C
> +#define MP_STATUS_OFFSET 0x10
> +#define BROADCAST_OFFSET 0x14
> +#define MASK_OFFSET      0x40
> +#define FORCE_OFFSET     0x80
> +#define EXTENDED_OFFSET  0xC0
> +
> +typedef struct IRQMP
> +{
> +    SysBusDevice busdev;
> +
> +    CPUSPARCState *env;
> +} IRQMP;
> +
> +typedef struct IRQMPState
> +{
> +    uint32_t level;
> +    uint32_t pending;
> +    uint32_t clear;
> +    uint32_t broadcast;
> +
> +    uint32_t mask[IRQMP_MAX_CPU];
> +    uint32_t force[IRQMP_MAX_CPU];
> +    uint32_t extended[IRQMP_MAX_CPU];
> +
> +    IRQMP    *parent;
> +} IRQMPState;
> +
> +IRQMPState grlib_irqmp_state;
> +
> +void grlib_irqmp_set_irq(void *opaque, int irq, int level);
> +
> +DeviceState *grlib_irqmp_create(target_phys_addr_t   base,
> +                                CPUState            *env,
> +                                qemu_irq           **cpu_irqs,
> +                                uint32_t             nr_irqs)
> +{
> +    DeviceState *dev;
> +
> +    assert(cpu_irqs != NULL);
> +
> +    dev = qdev_create(NULL, "grlib,irqmp");
> +    qdev_prop_set_ptr(dev, "cpustate", env);
> +
> +    if (qdev_init(dev)) {
> +        return NULL;
> +    }
> +
> +    sysbus_mmio_map(sysbus_from_qdev(dev), 0, base);
> +
> +    *cpu_irqs = qemu_allocate_irqs(grlib_irqmp_set_irq,
> +                                   &grlib_irqmp_state,
> +                                   nr_irqs);
> +
> +    return dev;
> +}
> +
> +static void grlib_irqmp_check_irqs(CPUState *env)
> +{
> +    uint32_t pend   = 0;
> +    uint32_t level0 = 0;
> +    uint32_t level1 = 0;
> +
> +    assert(env != NULL);
> +
> +    /* IRQ for CPU 0 (no SMP support) */
> +    pend = (grlib_irqmp_state.pending | grlib_irqmp_state.force[0])
> +        & grlib_irqmp_state.mask[0];
> +
> +
> +    level0 = pend & ~grlib_irqmp_state.level;
> +    level1 = pend &  grlib_irqmp_state.level;
> +
> +    DPRINTF("pend:0x%04x force:0x%04x mask:0x%04x lvl1:0x%04x lvl0:0x%04x\n",
> +            grlib_irqmp_state.pending, grlib_irqmp_state.force[0],
> +            grlib_irqmp_state.mask[0], level1, level0);
> +
> +    /* Trigger level1 interrupt first and level0 if there is no level1 */
> +    if (level1 != 0) {
> +        env->pil_in = level1;
> +    } else {
> +        env->pil_in = level0;
> +    }
> +
> +    if (env->pil_in && (env->interrupt_index == 0 ||
> +                        (env->interrupt_index & ~15) == TT_EXTINT)) {
> +        unsigned int i;
> +
> +        for (i = 15; i > 0; i--) {
> +            if (env->pil_in & (1 << i)) {
> +                int old_interrupt = env->interrupt_index;
> +
> +                env->interrupt_index = TT_EXTINT | i;
> +                if (old_interrupt != env->interrupt_index) {
> +                    DPRINTF("Set CPU IRQ %d\n", i);
> +                    cpu_interrupt(env, CPU_INTERRUPT_HARD);
> +                }
> +                break;
> +            }
> +        }
> +    } else if (!env->pil_in && (env->interrupt_index & ~15) == TT_EXTINT) {
> +        DPRINTF("Reset CPU IRQ %d\n", env->interrupt_index & 15);
> +        env->interrupt_index = 0;
> +        cpu_reset_interrupt(env, CPU_INTERRUPT_HARD);
> +    }
> +}
> +
> +void grlib_irqmp_ack(CPUSPARCState *env, int intno)
> +{
> +    assert(env != NULL);
> +
> +    uint32_t mask;
> +
> +    intno &= 15;
> +    mask = 1 << intno;
> +
> +    DPRINTF("grlib_irqmp_ack %d\n", intno);
> +
> +    /* Clear registers */
> +    grlib_irqmp_state.pending  &= ~mask;
> +    grlib_irqmp_state.force[0] &= ~mask; /* Only CPU 0 (No SMP support) */
> +
> +    grlib_irqmp_check_irqs(env);
> +}
> +
> +void grlib_irqmp_set_irq(void *opaque, int irq, int level)
> +{
> +    IRQMPState *s = opaque;
> +    int         i = 0;
> +
> +    assert(opaque != NULL);
> +    assert(s->parent != NULL);
> +
> +    if (level) {
> +        DPRINTF("Raise CPU IRQ %d\n", irq);
> +
> +        if (s->broadcast & 1 << irq) {
> +            /* Broadcasted IRQ */
> +            for (i = 0; i < IRQMP_MAX_CPU; i++) {
> +                s->force[i] |= 1 << irq;
> +            }
> +        } else {
> +            s->pending |= 1 << irq;
> +        }
> +        grlib_irqmp_check_irqs(s->parent->env);
> +
> +    } else {
> +
> +        DPRINTF("Lower CPU IRQ %d\n", irq);
> +        if (s->broadcast & 1 << irq) {
> +            /* Broadcasted IRQ */
> +            for (i = 0; i < IRQMP_MAX_CPU; i++) {
> +                s->force[i] &= ~(1 << irq);
> +            }
> +        } else {
> +            s->pending &= ~(1 << irq);
> +        }

If you use the edge triggered interrupt model in the devices, then you
shouldn't clear the pending bit here. A pulse from the device should
set it and it should only get cleared when the CPU acks it.

The model you've coded here indicates that the devices use a level
triggered approach. And the clearing of the pending bit in
grlib_irqmp_ack becomes meaningless...

Cheers