From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from [140.186.70.92] (port=52845 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1PV8lI-0003hy-Cv for qemu-devel@nongnu.org; Tue, 21 Dec 2010 15:24:45 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1PV8lG-0000Bd-Uk for qemu-devel@nongnu.org; Tue, 21 Dec 2010 15:24:44 -0500 Received: from mail-gy0-f173.google.com ([209.85.160.173]:39028) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1PV8lG-0000Aw-QT for qemu-devel@nongnu.org; Tue, 21 Dec 2010 15:24:42 -0500 Received: by gye5 with SMTP id 5so2193709gye.4 for ; Tue, 21 Dec 2010 12:24:38 -0800 (PST) From: "Adnan Khaleel" Message-ID: <20101221202429.27699a64@shadowfax.no-ip.com> Date: Tue, 21 Dec 2010 14:24:29 -0600 MIME-Version: 1.0 Content-Type: multipart/alternative; boundary="-----------cb3f37de3b8a7ea7e43e9b5f4dee80ad" Subject: [Qemu-devel] PCIe Transaction handling in Qemu Reply-To: adnan@khaleel.us List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: yamahata@valinux.co.jp This is a multi-part message in MIME format. -------------cb3f37de3b8a7ea7e43e9b5f4dee80ad Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Hello,=20 I have a question regarding how Qemu PCIe devices handle Config Transact= ions vs Memory Transactions (assuming the PCI device is setup to act as = PCI=5FBASE=5FADDRESS=5FSPACE=5FMEMORY). I'm using portions of hw/cirrus=5Fvga.c to make my point, static PCIDeviceInfo cirrus=5Fvga=5Finfo =3D { .qdev.name =3D "cirrus-vga", .qdev.desc =3D "Cirrus CLGD 54xx VGA", .qdev.size =3D sizeof(PCICirrusVGAState), .qdev.vmsd =3D &vmstate=5Fpci=5Fcirrus=5Fvga, .init =3D pci=5Fcirrus=5Fvga=5Finitfn, .romfile =3D VGABIOS=5FCIRRUS=5FFILENAME, .config=5Fwrite =3D pci=5Fcirrus=5Fwrite=5Fconfig, }; PCIDeviceInfo allows for custom .config=5Fwrite (& config=5Fread) handle= r as shown above. Any pci config operations operations initiated via leg= acy I/O operations will use these config handlers. The MMIO regions and handlers are mapped as shown below: static uint32=5Ft cirrus=5Fvga=5Fmem=5Freadb(void *opaque, target=5Fphys= =5Faddr=5Ft addr) { : } and so on for the other mmio handlers static CPUReadMemoryFunc * const cirrus=5Fvga=5Fmem=5Fread[3] =3D { cirrus=5Fvga=5Fmem=5Freadb, cirrus=5Fvga=5Fmem=5Freadw, cirrus=5Fvga=5Fmem=5Freadl, }; static CPUWriteMemoryFunc * const cirrus=5Fvga=5Fmem=5Fwrite[3] =3D { cirrus=5Fvga=5Fmem=5Fwriteb, cirrus=5Fvga=5Fmem=5Fwritew, cirrus=5Fvga=5Fmem=5Fwritel, }; static void cirrus=5Finit=5Fcommon(CirrusVGAState * s, int device=5Fid, = int is=5Fpci) { : : s->vga.vga=5Fio=5Fmemory =3D cpu=5Fregister=5Fio=5Fmemory(cirrus=5Fv= ga=5Fmem=5Fread, cirrus=5Fvga=5Fmem=5Fw= rite, s); : } static void cirrus=5Fpci=5Fmmio=5Fmap(PCIDevice *d, int region=5Fnum, pcibus=5Ft addr, pcibus=5Ft size, int type) { CirrusVGAState *s =3D &DO=5FUPCAST(PCICirrusVGAState, dev, d)->cirru= s=5Fvga; cpu=5Fregister=5Fphysical=5Fmemory(addr, CIRRUS=5FPNPMMIO=5FSIZE, s->cirrus=5Fmmio=5Fio=5Faddr); } static int pci=5Fcirrus=5Fvga=5Finitfn(PCIDevice *dev) { : : cirrus=5Finit=5Fcommon(..) : if (device=5Fid =3D=3D CIRRUS=5FID=5FCLGD5446) { pci=5Fregister=5Fbar((PCIDevice *)d, 1, CIRRUS=5FPNPMMIO=5FSIZE= , PCI=5FBASE=5FADDRESS=5FSPACE=5FMEMORY, cirrus= =5Fpci=5Fmmio=5Fmap); } return 0; } I have some questions about PCIe operations sssuming the device has MMIO= handlers involved (as shown above). 1. Will all PCIe config operations ALWAYS use the installed config handl= ers=3F Or can PCIe config operations use the MMIO handlers=3F 2. Assuming that both PCI config and MMIO operations can use the MMIO ha= ndlers, is there any way I can identify if a transaction is a config or = a memory transaction=3F 3.a. What address is passed on the MMIO handlers for config and MMIO ope= rations=3F From pci=5Fdata=5Fwrite in pci=5Fhost.c, it appears that conf= ig operations send only the offset into the config region. I couldn't de= termine what address is passed for MMIO operations. b. Is it an offset from the BAR for MMIO operations=3F c. How do I get the full physical address=3F d. What address does a PCIe device expect to see - physical or offset= for=3F e. Is there anyway I can find out what the bus and device numbers are= once inside the config and MMIO handlers=3F i.e once the execution has = reached the pci=5Fcirrus=5Fwrite=5Fconfig() or cirrus=5Fvga=5Fmem=5Fread= b(..) from the code above=3F Thanks Adnan -------------cb3f37de3b8a7ea7e43e9b5f4dee80ad Content-Type: text/html; charset="us-ascii" Content-Transfer-Encoding: quoted-printable Hello, 

I have a question regarding how Qemu PCI= e devices handle Config Transactions vs Memory Transactions (assuming th= e PCI device is setup to act as PCI=5FBASE=5FADDRESS=5FSPACE=5FMEMO= RY).

I'm using portions of hw/cirrus=5Fvga.c to= make my point,

static PCIDeviceInfo cirrus=5Fvga=5Finfo =3D {
 =    .qdev.name    =3D "cirrus-vga",
=     .qd= ev.desc    =3D "Cirrus CLGD 54xx VGA",
    .qdev.siz= e    =3D sizeof(PCICirrusVGAState),
    .qdev.vmsd &= nbsp;  =3D &vmstate=5Fpci=5Fcirrus=5Fvga,
    .init &= nbsp;       =3D pci=5Fcirrus=5Fvga=5Finitfn,
=
   &nbs= p;.romfile      =3D VGABIOS=5FCIRRUS=5FFILENAME,
   =  .config=5Fwrite =3D pci=5Fcirrus=5Fwrite=5Fconfig,
};

PCIDeviceInfo allo= ws for custom .config=5Fwrite (& config=5Fread) handler as shown abo= ve. Any pci config operations operations initiated via legacy I/O operat= ions will use these config handlers.

The MMIO regions and handlers are mapped a= s shown below:

stat= ic uint32=5Ft cirrus=5Fvga=5Fmem=5Freadb(void *opaque, target=5Fphys=5Fa= ddr=5Ft addr)
{
:
} and so on for the other mmio handlers

<= div style=3D"font-family: Tahoma, Verdana, sans-serif; ">
static CPUReadMemoryFunc * = const cirrus=5Fvga=5Fmem=5Fread[3] =3D {
    ci= rrus=5Fvga=5Fmem=5Freadb,
    cirrus=5Fvga=5Fme= m=5Freadw,
    cirrus=5Fvga=5Fmem=5Freadl,
};

static CPUWriteMemoryFunc * const cirr= us=5Fvga=5Fmem=5Fwrite[3] =3D {
    cirrus=5Fvg= a=5Fmem=5Fwriteb,
    cirrus=5Fvga=5Fmem=5Fwrit= ew,
    cirrus=5Fvga=5Fmem=5Fwritel,
= };

static void = cirrus=5Finit=5Fcommon(CirrusVGAState * s, int device=5Fid, int is=5Fpci= )
=
{
:
:
&nbs= p;   s->vga.vga=5Fio=5Fmemory =3D cpu=5Fregister=5Fio=5Fmem= ory(cirrus=5Fvga=5Fmem=5Fread,
       &nbs= p;                    =                     &= nbsp;cirrus=5Fvga=5Fmem=5Fwrite, s);
:
}

static void cirrus=5Fpci=5Fmmio=5Fmap(PCIDevice= *d, int region=5Fnum,
=09=09=09=09pcibus=5Ft addr, pcibus=5Ft size, int type)=
{
   &= nbsp;CirrusVGAState *s =3D &DO=5FUPCAST(PCICirrusVGAState, dev, d)-&= gt;cirrus=5Fvga;

    cpu=5Fregister=5Fphysical=5Fmemory(addr,= CIRRUS=5FPNPMMIO=5FSIZE,
=09=09=09=09 s->cirrus=5Fmmio=5Fio=5Faddr);
=
}

<= /div>
static = int pci=5Fcirrus=5Fvga=5Finitfn(PCIDevice *dev)
{
:<= /div>
:
     cirrus=5Finit=5Fcommon(..= )
:
     if (device=5Fid =3D=3D CIRRU= S=5FID=5FCLGD5446) {
         pci=5Fr= egister=5Fbar((PCIDevice *)d, 1, CIRRUS=5FPNPMMIO=5FSIZE,
&nbs= p;                    =      PCI=5FBASE=5FADDRESS=5FSPACE=5FMEMORY, cirrus=5Fpci= =5Fmmio=5Fmap);
     }
   &= nbsp; return 0;
}

I have= some questions about PCIe operations sssuming the device has MMIO handl= ers involved (as shown above).
1. Will all PCIe config operati= ons ALWAYS use the installed config handlers=3F Or can PCIe config opera= tions use the MMIO handlers=3F
2. Assuming that both PCI confi= g and MMIO operations can use the MMIO handlers, is there any way I can = identify if a transaction is a config or a memory transaction=3F
3.a. What address is passed on the MMIO handlers for config and MMIO = operations=3F From pci=5Fdata=5Fwrite in pci=5Fhost.c, it appears that c= onfig operations send only the offset into the config region. I couldn't= determine what address is passed for MMIO operations.
 &= nbsp; b. Is it an offset from the BAR for MMIO operations=3F
&= nbsp;  c. How do I get the full physical address=3F
 = ;  d. What address does a PCIe device expect to see - physical or o= ffset for=3F
   e. Is there anyway I can find out wh= at the bus and device numbers are once inside the config and MMIO handle= rs=3F i.e once the execution has reached the pci=5Fcirrus=5Fwrite=5Fconfi= g() or cirrus=5Fvga=5Fmem=5Freadb(..) from the code above=3F

Thanks

Adnan


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