Re: [Qemu-devel] [PATCH 3/3] tcg/arm: improve constant loading

[Aurelien Jarno <aurelien@aurel32.net>]

On Fri, Jan 07, 2011 at 01:52:25PM +0100, andrzej zaborowski wrote:
> Hi,
> 
> On 6 January 2011 22:54, Aurelien Jarno <aurelien@aurel32.net> wrote:
> > Improve constant loading in two ways:
> > - On all ARM versions, it's possible to load 0xffffff00 = -0x100 using
> >  the mvn rd, #0. Fix the conditions.
> > - On <= ARMv6 versions, where movw and movt are not available, load the
> >  constants using mov and orr with rotations depending on the constant
> >  to load. This is very useful for example to load constants where the
> >  low byte is 0. This reduce the generated code size by about 7%.
> 
> That's a nice improvement.  For some instructions using MVN and AND
> could yield even shorter code and I think with that the optimisation
> options (except loading from a constant pool) would be exhausted :)

I also did something with MVN and BIC, it works well, but the problem is
to find the right heuristic to choose between MOV/ORR and MVN/BIC. In my
tries, it was making the code bigger.

> ...
> >         }
> > +    } else {
> > +        int opc = ARITH_MOV;
> > +        int rn = 0;
> > +
> > +        do {
> > +            int i, rot;
> > +
> > +            i = ctz32(arg) & ~1;
> > +            rot = ((32 - i) << 7) & 0xf00;
> > +            tcg_out_dat_imm(s, cond, opc, rd, rn, ((arg >> i) & 0xff) | rot);
> > +            arg &= ~(0xff << i);
> > +
> > +            opc = ARITH_ORR;
> > +            rn = rd;
> 
> I think you could get rid of rn and just use rd from the start of the
> loop.  Otherwise acked by me too.
> 

What do you mean exactly? rn has to be 0 when opc is ARITH_MOV in order
to generate a correct ARM instruction.

-- 
Aurelien Jarno	                        GPG: 1024D/F1BCDB73
aurelien@aurel32.net                 http://www.aurel32.net