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From: Aurelien Jarno <aurelien@aurel32.net>
To: Peter Maydell <peter.maydell@linaro.org>
Cc: qemu-devel@nongnu.org
Subject: Re: [Qemu-devel] [PATCH 3/4] linux-user: ARM: clear the IT bits when invoking a signal handler
Date: Wed, 12 Jan 2011 00:09:25 +0100	[thread overview]
Message-ID: <20110111230925.GF2577@volta.aurel32.net> (raw)
In-Reply-To: <1294701112-14071-4-git-send-email-peter.maydell@linaro.org>

On Mon, Jan 10, 2011 at 11:11:51PM +0000, Peter Maydell wrote:
> When invoking a signal handler for an ARM target, make sure the IT
> bits in the CPSR are cleared. (This would otherwise cause incorrect
> execution if the IT state was non-zero when an exception occured.
> This bug has been masked previously because we weren't getting the
> IT state bits at exception entry right anyway.)
> 
> Also use the proper cpsr_read()/cpsr_write() interface to update
> the CPSR rather than manipulating CPUState fields directly.
> 
> Signed-off-by: Peter Maydell <peter.maydell@linaro.org>
> ---
>  linux-user/signal.c |   16 +++++++++-------
>  1 files changed, 9 insertions(+), 7 deletions(-)

Reviewed-by: Aurelien Jarno <aurelien@aurel32.net>

> diff --git a/linux-user/signal.c b/linux-user/signal.c
> index c846b8c..0664770 100644
> --- a/linux-user/signal.c
> +++ b/linux-user/signal.c
> @@ -1256,6 +1256,14 @@ setup_return(CPUState *env, struct target_sigaction *ka,
>  	abi_ulong handler = ka->_sa_handler;
>  	abi_ulong retcode;
>  	int thumb = handler & 1;
> +	uint32_t cpsr = cpsr_read(env);
> +
> +	cpsr &= ~CPSR_IT;
> +	if (thumb) {
> +		cpsr |= CPSR_T;
> +	} else {
> +		cpsr &= ~CPSR_T;
> +	}
>  
>  	if (ka->sa_flags & TARGET_SA_RESTORER) {
>  		retcode = ka->sa_restorer;
> @@ -1278,13 +1286,7 @@ setup_return(CPUState *env, struct target_sigaction *ka,
>  	env->regs[13] = frame_addr;
>  	env->regs[14] = retcode;
>  	env->regs[15] = handler & (thumb ? ~1 : ~3);
> -	env->thumb = thumb;
> -
> -#if 0
> -#ifdef TARGET_CONFIG_CPU_32
> -	env->cpsr = cpsr;
> -#endif
> -#endif
> +	cpsr_write(env, cpsr, 0xffffffff);
>  
>  	return 0;
>  }
> -- 
> 1.7.1
> 
> 
> 

-- 
Aurelien Jarno                          GPG: 1024D/F1BCDB73
aurelien@aurel32.net                 http://www.aurel32.net

  reply	other threads:[~2011-01-11 23:09 UTC|newest]

Thread overview: 10+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2011-01-10 23:11 [Qemu-devel] [PATCH 0/4] target-arm: get IT bits right at exceptions Peter Maydell
2011-01-10 23:11 ` [Qemu-devel] [PATCH 1/4] target-arm: Remove redundant setting of IT bits before Thumb SWI Peter Maydell
2011-01-11 23:06   ` Aurelien Jarno
2011-01-10 23:11 ` [Qemu-devel] [PATCH 2/4] target-arm: Refactor translation of exception generating instructions Peter Maydell
2011-01-11 23:07   ` Aurelien Jarno
2011-01-10 23:11 ` [Qemu-devel] [PATCH 3/4] linux-user: ARM: clear the IT bits when invoking a signal handler Peter Maydell
2011-01-11 23:09   ` Aurelien Jarno [this message]
2011-01-10 23:11 ` [Qemu-devel] [PATCH 4/4] target-arm: Restore IT bits when resuming after an exception Peter Maydell
2011-01-11 23:32   ` Aurelien Jarno
2011-01-14 19:40 ` [Qemu-devel] [PATCH 0/4] target-arm: get IT bits right at exceptions Aurelien Jarno

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