From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from [140.186.70.92] (port=48850 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1Pcxps-0007ch-AA for qemu-devel@nongnu.org; Wed, 12 Jan 2011 05:21:49 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Pcxpr-0004nz-4A for qemu-devel@nongnu.org; Wed, 12 Jan 2011 05:21:48 -0500 Received: from hall.aurel32.net ([88.191.126.93]:54361) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Pcxpq-0004mI-Vt for qemu-devel@nongnu.org; Wed, 12 Jan 2011 05:21:47 -0500 Date: Wed, 12 Jan 2011 11:21:39 +0100 From: Aurelien Jarno Subject: Re: [Qemu-devel] [PATCH 2/8] target-arm: Add symbolic constants for bitfields in TB flags Message-ID: <20110112102139.GF22287@hall.aurel32.net> References: <1294783938-19629-1-git-send-email-peter.maydell@linaro.org> <1294783938-19629-3-git-send-email-peter.maydell@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-15 Content-Disposition: inline In-Reply-To: <1294783938-19629-3-git-send-email-peter.maydell@linaro.org> Sender: Aurelien Jarno List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Peter Maydell Cc: qemu-devel@nongnu.org On Tue, Jan 11, 2011 at 10:12:12PM +0000, Peter Maydell wrote: > Add symbolic constants for the bitfields we use in the TB flags. > > Signed-off-by: Peter Maydell > --- > target-arm/cpu.h | 45 +++++++++++++++++++++++++++++++++++++++------ > 1 files changed, 39 insertions(+), 6 deletions(-) Reviewed-by: Aurelien Jarno > diff --git a/target-arm/cpu.h b/target-arm/cpu.h > index 340933e..3adb118 100644 > --- a/target-arm/cpu.h > +++ b/target-arm/cpu.h > @@ -440,17 +440,50 @@ static inline void cpu_clone_regs(CPUState *env, target_ulong newsp) > > #include "cpu-all.h" > > +/* Bit usage in the TB flags field: */ > +#define ARM_TBFLAG_THUMB_SHIFT 0 > +#define ARM_TBFLAG_THUMB_MASK (1 << ARM_TBFLAG_THUMB_SHIFT) > +#define ARM_TBFLAG_VECLEN_SHIFT 1 > +#define ARM_TBFLAG_VECLEN_MASK (0x7 << ARM_TBFLAG_VECLEN_SHIFT) > +#define ARM_TBFLAG_VECSTRIDE_SHIFT 4 > +#define ARM_TBFLAG_VECSTRIDE_MASK (0x3 << ARM_TBFLAG_VECSTRIDE_SHIFT) > +#define ARM_TBFLAG_PRIV_SHIFT 6 > +#define ARM_TBFLAG_PRIV_MASK (1 << ARM_TBFLAG_PRIV_SHIFT) > +#define ARM_TBFLAG_VFPEN_SHIFT 7 > +#define ARM_TBFLAG_VFPEN_MASK (1 << ARM_TBFLAG_VFPEN_SHIFT) > +#define ARM_TBFLAG_CONDEXEC_SHIFT 8 > +#define ARM_TBFLAG_CONDEXEC_MASK (0xff << ARM_TBFLAG_CONDEXEC_SHIFT) > +/* Bits 31..16 are currently unused. */ > + > +/* some convenience accessor macros */ > +#define ARM_TBFLAG_THUMB(F) \ > + (((F) & ARM_TBFLAG_THUMB_MASK) >> ARM_TBFLAG_THUMB_SHIFT) > +#define ARM_TBFLAG_VECLEN(F) \ > + (((F) & ARM_TBFLAG_VECLEN_MASK) >> ARM_TBFLAG_VECLEN_SHIFT) > +#define ARM_TBFLAG_VECSTRIDE(F) \ > + (((F) & ARM_TBFLAG_VECSTRIDE_MASK) >> ARM_TBFLAG_VECSTRIDE_SHIFT) > +#define ARM_TBFLAG_PRIV(F) \ > + (((F) & ARM_TBFLAG_PRIV_MASK) >> ARM_TBFLAG_PRIV_SHIFT) > +#define ARM_TBFLAG_VFPEN(F) \ > + (((F) & ARM_TBFLAG_VFPEN_MASK) >> ARM_TBFLAG_VFPEN_SHIFT) > +#define ARM_TBFLAG_CONDEXEC(F) \ > + (((F) & ARM_TBFLAG_CONDEXEC_MASK) >> ARM_TBFLAG_CONDEXEC_SHIFT) > + > static inline void cpu_get_tb_cpu_state(CPUState *env, target_ulong *pc, > target_ulong *cs_base, int *flags) > { > *pc = env->regs[15]; > *cs_base = 0; > - *flags = env->thumb | (env->vfp.vec_len << 1) > - | (env->vfp.vec_stride << 4) | (env->condexec_bits << 8); > - if ((env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) > - *flags |= (1 << 6); > - if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30)) > - *flags |= (1 << 7); > + *flags = (env->thumb << ARM_TBFLAG_THUMB_SHIFT) > + | (env->vfp.vec_len << ARM_TBFLAG_VECLEN_SHIFT) > + | (env->vfp.vec_stride << ARM_TBFLAG_VECSTRIDE_SHIFT) > + | (env->condexec_bits << ARM_TBFLAG_CONDEXEC_SHIFT); > + if ((env->uncached_cpsr & CPSR_M) != ARM_CPU_MODE_USR) { > + *flags |= ARM_TBFLAG_PRIV_MASK; > + } > + if (env->vfp.xregs[ARM_VFP_FPEXC] & (1 << 30)) { > + *flags |= ARM_TBFLAG_VFPEN_MASK; > + } > } > > #endif > -- > 1.6.3.3 > > > -- Aurelien Jarno GPG: 1024D/F1BCDB73 aurelien@aurel32.net http://www.aurel32.net