From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from [140.186.70.92] (port=50574 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1PezVR-0005Xi-Ly for qemu-devel@nongnu.org; Mon, 17 Jan 2011 19:33:06 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1PezVQ-0007u8-Ah for qemu-devel@nongnu.org; Mon, 17 Jan 2011 19:33:05 -0500 Received: from mail-ey0-f173.google.com ([209.85.215.173]:65344) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1PezVQ-0007u4-6C for qemu-devel@nongnu.org; Mon, 17 Jan 2011 19:33:04 -0500 Received: by eyg7 with SMTP id 7so3129228eyg.4 for ; Mon, 17 Jan 2011 16:33:03 -0800 (PST) Date: Tue, 18 Jan 2011 01:33:00 +0100 From: "Edgar E. Iglesias" Message-ID: <20110118003300.GA11846@laped.lan> References: <1295306982-29629-1-git-send-email-edgar.iglesias@gmail.com> <1295306982-29629-4-git-send-email-edgar.iglesias@gmail.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <1295306982-29629-4-git-send-email-edgar.iglesias@gmail.com> Subject: [Qemu-devel] Re: [PATCH 3/3] mips: Expire late timers when reading cp0_count List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: aurelien@aurel32.net On Tue, Jan 18, 2011 at 12:29:42AM +0100, edgar.iglesias@gmail.com wrote: > From: Edgar E. Iglesias > > When reading cp0_count from a timer with a late trigger that should > already have expired, expire it and raise the timer irq. > > This makes it possible for guest code (e.g, Linux) that first read > cp0_count, then compare it with cp0_compare and check for raised > timer interrupt lines to run reliably. > > Signed-off-by: Edgar E. Iglesias Sorry sent the wrong version of this one. It's supposed to be the following: commit 139330de404209528712fd703952c0b5ad4459a1 Author: Edgar E. Iglesias Date: Tue Jan 18 00:12:22 2011 +0100 mips: Expire late timers when reading cp0_count When reading cp0_count from a timer with a late trigger that should already have expired, expire it and raise the timer irq. This makes it possible for guest code (e.g, Linux) that first read cp0_count, then compare it with cp0_compare and check for raised timer interrupt lines to run reliably. Signed-off-by: Edgar E. Iglesias diff --git a/hw/mips_timer.c b/hw/mips_timer.c index 8c32087..9c95f28 100644 --- a/hw/mips_timer.c +++ b/hw/mips_timer.c @@ -69,9 +69,17 @@ uint32_t cpu_mips_get_count (CPUState *env) if (env->CP0_Cause & (1 << CP0Ca_DC)) { return env->CP0_Count; } else { + uint64_t now; + + now = qemu_get_clock(vm_clock); + if (qemu_timer_pending(env->timer) + && qemu_timer_expired(env->timer, now)) { + /* The timer has already expired. */ + cpu_mips_timer_expire(env); + } + return env->CP0_Count + - (uint32_t)muldiv64(qemu_get_clock(vm_clock), - TIMER_FREQ, get_ticks_per_sec()); + (uint32_t)muldiv64(now, TIMER_FREQ, get_ticks_per_sec()); } }