qemu-devel.nongnu.org archive mirror
 help / color / mirror / Atom feed
* [Qemu-devel] [PATCH 0/3] pci: disable intx on flr/bus reset
@ 2011-01-20  7:21 Isaku Yamahata
  2011-01-20  7:21 ` [Qemu-devel] [PATCH 1/3] pci: deassert intx on reset Isaku Yamahata
                   ` (3 more replies)
  0 siblings, 4 replies; 5+ messages in thread
From: Isaku Yamahata @ 2011-01-20  7:21 UTC (permalink / raw)
  To: qemu-devel; +Cc: yamahata, mst

So far pci_device_reset() is used for system reset.
In that case, interrupt controller is also reset so that
all irq is are deasserted.
But now pci bus reset/flr is supported, and in that case irq needs to be
disabled explicitly.

Isaku Yamahata (3):
  pci: deassert intx on reset.
  msi: simply write config a bit.
  msix: simply write config

 hw/msi.c  |    5 +----
 hw/msix.c |    5 +----
 hw/pci.c  |    9 +++++++++
 hw/pci.h  |    2 ++
 4 files changed, 13 insertions(+), 8 deletions(-)

^ permalink raw reply	[flat|nested] 5+ messages in thread

* [Qemu-devel] [PATCH 1/3] pci: deassert intx on reset.
  2011-01-20  7:21 [Qemu-devel] [PATCH 0/3] pci: disable intx on flr/bus reset Isaku Yamahata
@ 2011-01-20  7:21 ` Isaku Yamahata
  2011-01-20  7:21 ` [Qemu-devel] [PATCH 2/3] msi: simply write config a bit Isaku Yamahata
                   ` (2 subsequent siblings)
  3 siblings, 0 replies; 5+ messages in thread
From: Isaku Yamahata @ 2011-01-20  7:21 UTC (permalink / raw)
  To: qemu-devel; +Cc: yamahata, mst

deassert intx on device reset.
So far pci_device_reset() is used for system reset.
In that case, interrupt controller is reset at the same time so that
all irq is are deasserted.
But now pci bus reset/flr is supported, and in that case irq needs to be
disabled explicitly.

Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>
---
 hw/pci.c |    9 +++++++++
 hw/pci.h |    2 ++
 2 files changed, 11 insertions(+), 0 deletions(-)

diff --git a/hw/pci.c b/hw/pci.c
index e1e7b25..de6370f 100644
--- a/hw/pci.c
+++ b/hw/pci.c
@@ -137,6 +137,14 @@ static void pci_update_irq_status(PCIDevice *dev)
     }
 }
 
+void pci_device_deassert_intx(PCIDevice *dev)
+{
+    int i;
+    for (i = 0; i < PCI_NUM_PINS; ++i) {
+        qemu_set_irq(dev->irq[i], 0);
+    }
+}
+
 /*
  * This function is called on #RST and FLR.
  * FLR if PCI_EXP_DEVCTL_BCR_FLR is set
@@ -152,6 +160,7 @@ void pci_device_reset(PCIDevice *dev)
 
     dev->irq_state = 0;
     pci_update_irq_status(dev);
+    pci_device_deassert_intx(dev);
     /* Clear all writeable bits */
     pci_word_test_and_clear_mask(dev->config + PCI_COMMAND,
                                  pci_get_word(dev->wmask + PCI_COMMAND) |
diff --git a/hw/pci.h b/hw/pci.h
index a0fd953..01c3285 100644
--- a/hw/pci.h
+++ b/hw/pci.h
@@ -265,6 +265,8 @@ void do_pci_info_print(Monitor *mon, const QObject *data);
 void do_pci_info(Monitor *mon, QObject **ret_data);
 void pci_bridge_update_mappings(PCIBus *b);
 
+void pci_device_deassert_intx(PCIDevice *dev);
+
 static inline void
 pci_set_byte(uint8_t *config, uint8_t val)
 {
-- 
1.7.1.1

^ permalink raw reply related	[flat|nested] 5+ messages in thread

* [Qemu-devel] [PATCH 2/3] msi: simply write config a bit.
  2011-01-20  7:21 [Qemu-devel] [PATCH 0/3] pci: disable intx on flr/bus reset Isaku Yamahata
  2011-01-20  7:21 ` [Qemu-devel] [PATCH 1/3] pci: deassert intx on reset Isaku Yamahata
@ 2011-01-20  7:21 ` Isaku Yamahata
  2011-01-20  7:21 ` [Qemu-devel] [PATCH 3/3] msix: simply write config Isaku Yamahata
  2011-01-20  9:10 ` [Qemu-devel] Re: [PATCH 0/3] pci: disable intx on flr/bus reset Michael S. Tsirkin
  3 siblings, 0 replies; 5+ messages in thread
From: Isaku Yamahata @ 2011-01-20  7:21 UTC (permalink / raw)
  To: qemu-devel; +Cc: yamahata, mst

use pci_device_deassert_intx().

Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>
---
 hw/msi.c |    5 +----
 1 files changed, 1 insertions(+), 4 deletions(-)

diff --git a/hw/msi.c b/hw/msi.c
index f03f519..3dc3a24 100644
--- a/hw/msi.c
+++ b/hw/msi.c
@@ -255,7 +255,6 @@ void msi_write_config(PCIDevice *dev, uint32_t addr, uint32_t val, int len)
     uint8_t log_max_vecs;
     unsigned int vector;
     uint32_t pending;
-    int i;
 
     if (!ranges_overlap(addr, len, dev->msi_cap, msi_cap_sizeof(flags))) {
         return;
@@ -296,9 +295,7 @@ void msi_write_config(PCIDevice *dev, uint32_t addr, uint32_t val, int len)
      *   from using its INTx# pin (if implemented) to request
      *   service (MSI, MSI-X, and INTx# are mutually exclusive).
      */
-    for (i = 0; i < PCI_NUM_PINS; ++i) {
-        qemu_set_irq(dev->irq[i], 0);
-    }
+    pci_device_deassert_intx(dev);
 
     /*
      * nr_vectors might be set bigger than capable. So clamp it.
-- 
1.7.1.1

^ permalink raw reply related	[flat|nested] 5+ messages in thread

* [Qemu-devel] [PATCH 3/3] msix: simply write config
  2011-01-20  7:21 [Qemu-devel] [PATCH 0/3] pci: disable intx on flr/bus reset Isaku Yamahata
  2011-01-20  7:21 ` [Qemu-devel] [PATCH 1/3] pci: deassert intx on reset Isaku Yamahata
  2011-01-20  7:21 ` [Qemu-devel] [PATCH 2/3] msi: simply write config a bit Isaku Yamahata
@ 2011-01-20  7:21 ` Isaku Yamahata
  2011-01-20  9:10 ` [Qemu-devel] Re: [PATCH 0/3] pci: disable intx on flr/bus reset Michael S. Tsirkin
  3 siblings, 0 replies; 5+ messages in thread
From: Isaku Yamahata @ 2011-01-20  7:21 UTC (permalink / raw)
  To: qemu-devel; +Cc: yamahata, mst

use pci_device_deassert_intx().

Signed-off-by: Isaku Yamahata <yamahata@valinux.co.jp>
---
 hw/msix.c |    5 +----
 1 files changed, 1 insertions(+), 4 deletions(-)

diff --git a/hw/msix.c b/hw/msix.c
index e123082..daaf9b7 100644
--- a/hw/msix.c
+++ b/hw/msix.c
@@ -159,7 +159,6 @@ void msix_write_config(PCIDevice *dev, uint32_t addr,
 {
     unsigned enable_pos = dev->msix_cap + MSIX_CONTROL_OFFSET;
     int vector;
-    int i;
 
     if (!range_covers_byte(addr, len, enable_pos)) {
         return;
@@ -169,9 +168,7 @@ void msix_write_config(PCIDevice *dev, uint32_t addr,
         return;
     }
 
-    for (i = 0; i < PCI_NUM_PINS; ++i) {
-        qemu_set_irq(dev->irq[i], 0);
-    }
+    pci_device_deassert_intx(dev);
 
     if (msix_function_masked(dev)) {
         return;
-- 
1.7.1.1

^ permalink raw reply related	[flat|nested] 5+ messages in thread

* [Qemu-devel] Re: [PATCH 0/3] pci: disable intx on flr/bus reset
  2011-01-20  7:21 [Qemu-devel] [PATCH 0/3] pci: disable intx on flr/bus reset Isaku Yamahata
                   ` (2 preceding siblings ...)
  2011-01-20  7:21 ` [Qemu-devel] [PATCH 3/3] msix: simply write config Isaku Yamahata
@ 2011-01-20  9:10 ` Michael S. Tsirkin
  3 siblings, 0 replies; 5+ messages in thread
From: Michael S. Tsirkin @ 2011-01-20  9:10 UTC (permalink / raw)
  To: Isaku Yamahata; +Cc: qemu-devel

On Thu, Jan 20, 2011 at 04:21:37PM +0900, Isaku Yamahata wrote:
> So far pci_device_reset() is used for system reset.
> In that case, interrupt controller is also reset so that
> all irq is are deasserted.
> But now pci bus reset/flr is supported, and in that case irq needs to be
> disabled explicitly.

Simply->simplify
Otherwise looks good. Applied, thanks!

> Isaku Yamahata (3):
>   pci: deassert intx on reset.
>   msi: simply write config a bit.
>   msix: simply write config
> 
>  hw/msi.c  |    5 +----
>  hw/msix.c |    5 +----
>  hw/pci.c  |    9 +++++++++
>  hw/pci.h  |    2 ++
>  4 files changed, 13 insertions(+), 8 deletions(-)

^ permalink raw reply	[flat|nested] 5+ messages in thread

end of thread, other threads:[~2011-01-20  9:12 UTC | newest]

Thread overview: 5+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2011-01-20  7:21 [Qemu-devel] [PATCH 0/3] pci: disable intx on flr/bus reset Isaku Yamahata
2011-01-20  7:21 ` [Qemu-devel] [PATCH 1/3] pci: deassert intx on reset Isaku Yamahata
2011-01-20  7:21 ` [Qemu-devel] [PATCH 2/3] msi: simply write config a bit Isaku Yamahata
2011-01-20  7:21 ` [Qemu-devel] [PATCH 3/3] msix: simply write config Isaku Yamahata
2011-01-20  9:10 ` [Qemu-devel] Re: [PATCH 0/3] pci: disable intx on flr/bus reset Michael S. Tsirkin

This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).