* [Qemu-devel] [PATCH] target-sh4: fix index of address read error exception
@ 2011-01-25 4:51 Alexandre Courbot
2011-01-25 4:51 ` [Qemu-devel] [PATCH] target-sh4: update PTEH upon MMU exception Alexandre Courbot
2011-01-25 8:03 ` [Qemu-devel] [PATCH] target-sh4: fix index of address read error exception Aurelien Jarno
0 siblings, 2 replies; 6+ messages in thread
From: Alexandre Courbot @ 2011-01-25 4:51 UTC (permalink / raw)
To: Aurelien Jarno; +Cc: Alexandre Courbot, qemu-devel
Exception index of address read error should be 0x0e0.
---
target-sh4/helper.c | 2 +-
1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/target-sh4/helper.c b/target-sh4/helper.c
index 45449ea..2d76f22 100644
--- a/target-sh4/helper.c
+++ b/target-sh4/helper.c
@@ -479,7 +479,7 @@ int cpu_sh4_handle_mmu_fault(CPUState * env, target_ulong address, int rw,
break;
case MMU_IADDR_ERROR:
case MMU_DADDR_ERROR_READ:
- env->exception_index = 0x0c0;
+ env->exception_index = 0x0e0;
break;
case MMU_DADDR_ERROR_WRITE:
env->exception_index = 0x100;
--
1.7.3.5
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [Qemu-devel] [PATCH] target-sh4: update PTEH upon MMU exception
2011-01-25 4:51 [Qemu-devel] [PATCH] target-sh4: fix index of address read error exception Alexandre Courbot
@ 2011-01-25 4:51 ` Alexandre Courbot
2011-01-25 8:05 ` Aurelien Jarno
2011-01-25 8:03 ` [Qemu-devel] [PATCH] target-sh4: fix index of address read error exception Aurelien Jarno
1 sibling, 1 reply; 6+ messages in thread
From: Alexandre Courbot @ 2011-01-25 4:51 UTC (permalink / raw)
To: Aurelien Jarno; +Cc: Alexandre Courbot, qemu-devel
Update the PTEH register to contain the VPN at which an MMU
exception occured as specified by the SH4 reference.
---
target-sh4/helper.c | 3 +++
1 files changed, 3 insertions(+), 0 deletions(-)
diff --git a/target-sh4/helper.c b/target-sh4/helper.c
index 2d76f22..c34d2f5 100644
--- a/target-sh4/helper.c
+++ b/target-sh4/helper.c
@@ -453,6 +453,9 @@ int cpu_sh4_handle_mmu_fault(CPUState * env, target_ulong address, int rw,
if (ret != MMU_OK) {
env->tea = address;
+ if (ret != MMU_DTLB_MULTIPLE && ret != MMU_ITLB_MULTIPLE)
+ env->pteh = (env->pteh & PTEH_ASID_MASK) |
+ (address & PTEH_VPN_MASK);
switch (ret) {
case MMU_ITLB_MISS:
case MMU_DTLB_MISS_READ:
--
1.7.3.5
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [Qemu-devel] [PATCH] target-sh4: fix index of address read error exception
2011-01-25 4:51 [Qemu-devel] [PATCH] target-sh4: fix index of address read error exception Alexandre Courbot
2011-01-25 4:51 ` [Qemu-devel] [PATCH] target-sh4: update PTEH upon MMU exception Alexandre Courbot
@ 2011-01-25 8:03 ` Aurelien Jarno
1 sibling, 0 replies; 6+ messages in thread
From: Aurelien Jarno @ 2011-01-25 8:03 UTC (permalink / raw)
To: Alexandre Courbot; +Cc: qemu-devel
On Tue, Jan 25, 2011 at 01:51:16PM +0900, Alexandre Courbot wrote:
> Exception index of address read error should be 0x0e0.
> ---
> target-sh4/helper.c | 2 +-
> 1 files changed, 1 insertions(+), 1 deletions(-)
>
> diff --git a/target-sh4/helper.c b/target-sh4/helper.c
> index 45449ea..2d76f22 100644
> --- a/target-sh4/helper.c
> +++ b/target-sh4/helper.c
> @@ -479,7 +479,7 @@ int cpu_sh4_handle_mmu_fault(CPUState * env, target_ulong address, int rw,
> break;
> case MMU_IADDR_ERROR:
> case MMU_DADDR_ERROR_READ:
> - env->exception_index = 0x0c0;
> + env->exception_index = 0x0e0;
> break;
> case MMU_DADDR_ERROR_WRITE:
> env->exception_index = 0x100;
Thanks, applied.
--
Aurelien Jarno GPG: 1024D/F1BCDB73
aurelien@aurel32.net http://www.aurel32.net
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [Qemu-devel] [PATCH] target-sh4: update PTEH upon MMU exception
2011-01-25 4:51 ` [Qemu-devel] [PATCH] target-sh4: update PTEH upon MMU exception Alexandre Courbot
@ 2011-01-25 8:05 ` Aurelien Jarno
2011-01-26 2:57 ` [Qemu-devel] [PATCH v2] " Alexandre Courbot
0 siblings, 1 reply; 6+ messages in thread
From: Aurelien Jarno @ 2011-01-25 8:05 UTC (permalink / raw)
To: Alexandre Courbot; +Cc: qemu-devel
On Tue, Jan 25, 2011 at 01:51:17PM +0900, Alexandre Courbot wrote:
> Update the PTEH register to contain the VPN at which an MMU
> exception occured as specified by the SH4 reference.
> ---
> target-sh4/helper.c | 3 +++
> 1 files changed, 3 insertions(+), 0 deletions(-)
>
> diff --git a/target-sh4/helper.c b/target-sh4/helper.c
> index 2d76f22..c34d2f5 100644
> --- a/target-sh4/helper.c
> +++ b/target-sh4/helper.c
> @@ -453,6 +453,9 @@ int cpu_sh4_handle_mmu_fault(CPUState * env, target_ulong address, int rw,
>
> if (ret != MMU_OK) {
> env->tea = address;
> + if (ret != MMU_DTLB_MULTIPLE && ret != MMU_ITLB_MULTIPLE)
> + env->pteh = (env->pteh & PTEH_ASID_MASK) |
> + (address & PTEH_VPN_MASK);
The code in itself is correct, however you should follow CODING_STYLE
and write the if the following way:
if () {
}
> switch (ret) {
> case MMU_ITLB_MISS:
> case MMU_DTLB_MISS_READ:
> --
> 1.7.3.5
>
>
>
--
Aurelien Jarno GPG: 1024D/F1BCDB73
aurelien@aurel32.net http://www.aurel32.net
^ permalink raw reply [flat|nested] 6+ messages in thread
* [Qemu-devel] [PATCH v2] target-sh4: update PTEH upon MMU exception
2011-01-25 8:05 ` Aurelien Jarno
@ 2011-01-26 2:57 ` Alexandre Courbot
2011-01-26 13:31 ` Aurelien Jarno
0 siblings, 1 reply; 6+ messages in thread
From: Alexandre Courbot @ 2011-01-26 2:57 UTC (permalink / raw)
To: Aurelien Jarno; +Cc: Alexandre Courbot, qemu-devel
Update the PTEH register to contain the VPN at which an MMU
exception occured as specified by the SH4 reference.
Signed-off-by: Alexandre Courbot <gnurou@gmail.com>
---
target-sh4/helper.c | 4 ++++
1 files changed, 4 insertions(+), 0 deletions(-)
diff --git a/target-sh4/helper.c b/target-sh4/helper.c
index 19b309b..8f8c66c 100644
--- a/target-sh4/helper.c
+++ b/target-sh4/helper.c
@@ -453,6 +453,10 @@ int cpu_sh4_handle_mmu_fault(CPUState * env, target_ulong address, int rw,
if (ret != MMU_OK) {
env->tea = address;
+ if (ret != MMU_DTLB_MULTIPLE && ret != MMU_ITLB_MULTIPLE) {
+ env->pteh = (env->pteh & PTEH_ASID_MASK) |
+ (address & PTEH_VPN_MASK);
+ }
switch (ret) {
case MMU_ITLB_MISS:
case MMU_DTLB_MISS_READ:
--
1.7.3.5
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [Qemu-devel] [PATCH v2] target-sh4: update PTEH upon MMU exception
2011-01-26 2:57 ` [Qemu-devel] [PATCH v2] " Alexandre Courbot
@ 2011-01-26 13:31 ` Aurelien Jarno
0 siblings, 0 replies; 6+ messages in thread
From: Aurelien Jarno @ 2011-01-26 13:31 UTC (permalink / raw)
To: Alexandre Courbot; +Cc: qemu-devel
On Wed, Jan 26, 2011 at 11:57:53AM +0900, Alexandre Courbot wrote:
> Update the PTEH register to contain the VPN at which an MMU
> exception occured as specified by the SH4 reference.
>
> Signed-off-by: Alexandre Courbot <gnurou@gmail.com>
> ---
> target-sh4/helper.c | 4 ++++
> 1 files changed, 4 insertions(+), 0 deletions(-)
Thanks, applied.
> diff --git a/target-sh4/helper.c b/target-sh4/helper.c
> index 19b309b..8f8c66c 100644
> --- a/target-sh4/helper.c
> +++ b/target-sh4/helper.c
> @@ -453,6 +453,10 @@ int cpu_sh4_handle_mmu_fault(CPUState * env, target_ulong address, int rw,
>
> if (ret != MMU_OK) {
> env->tea = address;
> + if (ret != MMU_DTLB_MULTIPLE && ret != MMU_ITLB_MULTIPLE) {
> + env->pteh = (env->pteh & PTEH_ASID_MASK) |
> + (address & PTEH_VPN_MASK);
> + }
> switch (ret) {
> case MMU_ITLB_MISS:
> case MMU_DTLB_MISS_READ:
> --
> 1.7.3.5
>
>
>
--
Aurelien Jarno GPG: 1024D/F1BCDB73
aurelien@aurel32.net http://www.aurel32.net
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2011-01-26 13:31 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz follow: Atom feed
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2011-01-25 4:51 [Qemu-devel] [PATCH] target-sh4: fix index of address read error exception Alexandre Courbot
2011-01-25 4:51 ` [Qemu-devel] [PATCH] target-sh4: update PTEH upon MMU exception Alexandre Courbot
2011-01-25 8:05 ` Aurelien Jarno
2011-01-26 2:57 ` [Qemu-devel] [PATCH v2] " Alexandre Courbot
2011-01-26 13:31 ` Aurelien Jarno
2011-01-25 8:03 ` [Qemu-devel] [PATCH] target-sh4: fix index of address read error exception Aurelien Jarno
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