From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from [140.186.70.92] (port=50237 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1PiIwT-0002JF-94 for qemu-devel@nongnu.org; Wed, 26 Jan 2011 22:54:42 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1PiIvu-0006Jh-Jy for qemu-devel@nongnu.org; Wed, 26 Jan 2011 22:54:07 -0500 Received: from mail.valinux.co.jp ([210.128.90.3]:42899) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1PiIvu-0006JZ-28 for qemu-devel@nongnu.org; Wed, 26 Jan 2011 22:54:06 -0500 Date: Thu, 27 Jan 2011 12:54:03 +0900 From: Isaku Yamahata Message-ID: <20110127035403.GD4395@valinux.co.jp> References: <426869a882ff2ab059e7c49e87862658cc29d62c.1296035044.git.yamahata@valinux.co.jp> <20110126120959.GB11913@redhat.com> <20110126131748.GA4395@valinux.co.jp> <20110126134601.GE12805@redhat.com> <20110126135342.GB4395@valinux.co.jp> <20110126135715.GB13219@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20110126135715.GB13219@redhat.com> Subject: [Qemu-devel] Re: [PATCH] pci: w1cmask[PCI_BRIDGE_CONTROL] initialized incorrectly List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: "Michael S. Tsirkin" Cc: qemu-devel@nongnu.org On Wed, Jan 26, 2011 at 03:57:15PM +0200, Michael S. Tsirkin wrote: > On Wed, Jan 26, 2011 at 10:53:42PM +0900, Isaku Yamahata wrote: > > On Wed, Jan 26, 2011 at 03:46:01PM +0200, Michael S. Tsirkin wrote: > > > On Wed, Jan 26, 2011 at 10:17:48PM +0900, Isaku Yamahata wrote: > > > > The bit should be writable, not w1c. > > > > > > > > 3.2.5.18 bridge control register > > > > bit 11 Discard Timer SERR# Enable > > > > > > > > When set to 1, this bit enables the bridge to assert SERR# on > > > > the primary interface when either the Primary Discard Timer or > > > > Secondary Discard Timer expires and a Delayed Transaction is > > > > discarded from a queue in the bridge. The default state of this > > > > bit must be 0 after reset. > > > > 0 - do not assert SERR# on the primary interface as > > > > a result of the expiration of either the Primary > > > > Discard Timer or Secondary Discard Timer > > > > 1 - assert SERR# on the primary interface if either > > > > the Primary Discard Timer or Secondary Discard > > > > Timer expires and a Delayed Transaction > > > > > > Yes but > > > #define PCI_BRIDGE_CTL_DISCARD_STATUS 0x400 /* Discard timer status */ > > > > > > So this is bit 10? > > > > Oh, sorry. So wmask should be chenged. > > Yes. does the below work? Yep. Thank you. Tested-by: Isaku Yamahata > > commit 24ebb78e6ec19b39cd138d493a2859122110f9cb > Author: Michael S. Tsirkin > Date: Wed Jan 26 15:55:07 2011 +0200 > > pci: bridge control fixup > > PCI_BRIDGE_CTL_DISCARD_STATUS (bit 10 in bridge control register) > is W1C so we should not make it writeable, otherwise the assert(!(wmask > & w1cmask)) in pci_default_write_config() is hit > > Signed-off-by: Michael S. Tsirkin > Reported-by: Isaku Yamahata > > diff --git a/hw/pci.c b/hw/pci.c > index 044c4bd..712280a 100644 > --- a/hw/pci.c > +++ b/hw/pci.c > @@ -641,7 +641,6 @@ static void pci_init_wmask_bridge(PCIDevice *d) > PCI_BRIDGE_CTL_FAST_BACK | > PCI_BRIDGE_CTL_DISCARD | > PCI_BRIDGE_CTL_SEC_DISCARD | > - PCI_BRIDGE_CTL_DISCARD_STATUS | > PCI_BRIDGE_CTL_DISCARD_SERR); > /* Below does not do anything as we never set this bit, put here for > * completeness. */ > -- yamahata