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From: Michael Walle <michael@walle.cc>
Subject: Re: [Qemu-devel] [PATCH 09/17] lm32: timer model
Date: Fri, 11 Feb 2011 23:29:31 +0100
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To: Blue Swirl <blauwirbel@gmail.com>
Cc: "Edgar E. Iglesias" <edgar.iglesias@gmail.com>, Richard Henderson <rth@twiddle.net>, qemu-devel@nongnu.org, Alexander Graf <agraf@suse.de>

Am Freitag 11 Februar 2011, 22:22:32 schrieb Blue Swirl:
> > +static uint32_t timer_read(void *opaque, target_phys_addr_t addr)
> > +{
> > +    LM32TimerState *s = opaque;
> > +    uint32_t r = 0;
> > +
> > +    addr >>= 2;
> > +    switch (addr) {
> > +    case R_SR:
> > +    case R_CR:
> > +    case R_PERIOD:
> > +        r = s->regs[addr];
> > +        break;
> > +    case R_SNAPSHOT:
> > +        r = (uint32_t)ptimer_get_count(s->ptimer);
> > +        break;
> > +
> > +    default:
> > +        hw_error("lm32_timer: read access to unkown register 0x"
> > +                TARGET_FMT_plx, addr << 2);
> 
> Insecure, please fix also others.
Many devices in hw/ treat memory access to unknown registers in that way. Are 
there any 'good' example models, where i can look at? I guess i should print a 
warning instead?

-- 
Michael