From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from [140.186.70.92] (port=57510 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1PpITa-0005XS-E6 for qemu-devel@nongnu.org; Tue, 15 Feb 2011 05:49:47 -0500 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1PpITZ-0003j5-6y for qemu-devel@nongnu.org; Tue, 15 Feb 2011 05:49:46 -0500 Received: from os.inf.tu-dresden.de ([141.76.48.99]:38260) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1PpITY-0003iz-UR for qemu-devel@nongnu.org; Tue, 15 Feb 2011 05:49:45 -0500 Received: from erwin.inf.tu-dresden.de ([141.76.48.80] helo=os.inf.tu-dresden.de) by os.inf.tu-dresden.de with esmtps (TLSv1:AES128-SHA:128) (Exim 4.74) id 1PpITX-0003Ag-Qg for qemu-devel@nongnu.org; Tue, 15 Feb 2011 11:49:44 +0100 Date: Tue, 15 Feb 2011 11:49:42 +0100 From: Adam Lackorzynski Message-ID: <20110215104942.GD19666@os.inf.tu-dresden.de> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Subject: [Qemu-devel] [PATCH 3/3] target-arm: Implement cp15 VA->PA translation List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Implement VA->PA translations by cp15-c7 that went through unchanged previously. Signed-off-by: Adam Lackorzynski --- target-arm/cpu.h | 1 + target-arm/helper.c | 51 +++++++++++++++++++++++++++++++++++++++++++++++++-- 2 files changed, 50 insertions(+), 2 deletions(-) diff --git a/target-arm/cpu.h b/target-arm/cpu.h index c9febfa..603574b 100644 --- a/target-arm/cpu.h +++ b/target-arm/cpu.h @@ -126,6 +126,7 @@ typedef struct CPUARMState { uint32_t c6_region[8]; /* MPU base/size registers. */ uint32_t c6_insn; /* Fault address registers. */ uint32_t c6_data; + uint32_t c7_par; /* Translation result. */ uint32_t c9_insn; /* Cache lockdown registers. */ uint32_t c9_data; uint32_t c13_fcse; /* FCSE PID. */ diff --git a/target-arm/helper.c b/target-arm/helper.c index 7f63a28..32cc795 100644 --- a/target-arm/helper.c +++ b/target-arm/helper.c @@ -1456,8 +1456,52 @@ void HELPER(set_cp15)(CPUState *env, uint32_t insn, uint32_t val) case 7: /* Cache control. */ env->cp15.c15_i_max = 0x000; env->cp15.c15_i_min = 0xff0; - /* No cache, so nothing to do. */ - /* ??? MPCore has VA to PA translation functions. */ + /* No cache, so nothing to do except VA->PA translations. */ + if (arm_feature(env, ARM_FEATURE_V6)) { + switch (crm) { + case 4: + env->cp15.c7_par = val; + break; + case 8: { + uint32_t phys_addr; + target_ulong page_size; + int prot; + int ret, is_user; + int access_type; + + switch (op2) { + case 0: /* priv read */ + is_user = 0; + access_type = 0; + break; + case 1: /* priv write */ + is_user = 0; + access_type = 1; + break; + case 2: /* user read */ + is_user = 1; + access_type = 0; + break; + case 3: /* user write */ + is_user = 1; + access_type = 1; + break; + default: /* 4-7 are only available with TZ */ + goto bad_reg; + } + ret = get_phys_addr_v6(env, val, access_type, is_user, + &phys_addr, &prot, &page_size); + if (ret == 0) { + env->cp15.c7_par = phys_addr; + if (page_size > TARGET_PAGE_SIZE) + env->cp15.c7_par |= 1 << 1; + } else { + env->cp15.c7_par = ret | 1; + } + break; + } + } + } break; case 8: /* MMU TLB control. */ switch (op2) { @@ -1789,6 +1833,9 @@ uint32_t HELPER(get_cp15)(CPUState *env, uint32_t insn) } } case 7: /* Cache control. */ + if (crm == 4 && op2 == 0) { + return env->cp15.c7_par; + } /* FIXME: Should only clear Z flag if destination is r15. */ env->ZF = 0; return 0; -- 1.7.2.3 Adam -- Adam adam@os.inf.tu-dresden.de Lackorzynski http://os.inf.tu-dresden.de/~adam/