From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from [140.186.70.92] (port=46497 helo=eggs.gnu.org) by lists.gnu.org with esmtp (Exim 4.43) id 1Q1xaw-0008Ma-Me for qemu-devel@nongnu.org; Tue, 22 Mar 2011 05:09:43 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Q1xav-0000wV-Ej for qemu-devel@nongnu.org; Tue, 22 Mar 2011 05:09:42 -0400 Received: from hall.aurel32.net ([88.191.126.93]:37124) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Q1xav-0000vy-AG for qemu-devel@nongnu.org; Tue, 22 Mar 2011 05:09:41 -0400 Date: Tue, 22 Mar 2011 10:09:29 +0100 From: Aurelien Jarno Subject: Re: [Qemu-devel] Re: [PATCH] target-ppc: ext32u instead of andi with constant Message-ID: <20110322090929.GA11876@ohm.aurel32.net> References: <1300776089-5713-1-git-send-email-aurelien@aurel32.net> <9BC3A67A-7FA5-4033-B722-7D0404F1D3B5@suse.de> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-15 Content-Disposition: inline In-Reply-To: <9BC3A67A-7FA5-4033-B722-7D0404F1D3B5@suse.de> List-Id: qemu-devel.nongnu.org List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Alexander Graf Cc: qemu-devel@nongnu.org On Tue, Mar 22, 2011 at 08:36:26AM +0100, Alexander Graf wrote: > > On 22.03.2011, at 07:41, Aurelien Jarno wrote: > > > Cc: Alexander Graf > > Signed-off-by: Aurelien Jarno > > --- > > target-ppc/translate.c | 8 ++++---- > > 1 files changed, 4 insertions(+), 4 deletions(-) > > > > diff --git a/target-ppc/translate.c b/target-ppc/translate.c > > index 3d265e3..49eab28 100644 > > --- a/target-ppc/translate.c > > +++ b/target-ppc/translate.c > > @@ -6975,7 +6975,7 @@ static inline void gen_evmergelo(DisasContext *ctx) > > #if defined(TARGET_PPC64) > > TCGv t0 = tcg_temp_new(); > > TCGv t1 = tcg_temp_new(); > > - tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x00000000FFFFFFFFLL); > > + tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]); > > tcg_gen_shli_tl(t1, cpu_gpr[rA(ctx->opcode)], 32); > > tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1); > > tcg_temp_free(t0); > > @@ -6994,7 +6994,7 @@ static inline void gen_evmergehilo(DisasContext *ctx) > > #if defined(TARGET_PPC64) > > TCGv t0 = tcg_temp_new(); > > TCGv t1 = tcg_temp_new(); > > - tcg_gen_andi_tl(t0, cpu_gpr[rB(ctx->opcode)], 0x00000000FFFFFFFFLL); > > + tcg_gen_ext32u_tl(t0, cpu_gpr[rB(ctx->opcode)]); > > tcg_gen_andi_tl(t1, cpu_gpr[rA(ctx->opcode)], 0xFFFFFFFF0000000ULL); > > Wouldn't deposit make sense here? But that can be a later optimization. Indeed it makes sense here, the thing is that I don't really know how deposit is going. We have merged it, but we don't have the expected performance (ie no improvement). > > tcg_gen_or_tl(cpu_gpr[rD(ctx->opcode)], t0, t1); > > tcg_temp_free(t0); > > @@ -7083,14 +7083,14 @@ static inline void gen_evsel(DisasContext *ctx) > > tcg_gen_andi_i32(t0, cpu_crf[ctx->opcode & 0x07], 1 << 2); > > tcg_gen_brcondi_i32(TCG_COND_EQ, t0, 0, l3); > > #if defined(TARGET_PPC64) > > - tcg_gen_andi_tl(t2, cpu_gpr[rA(ctx->opcode)], 0x00000000FFFFFFFFULL); > > + tcg_gen_ext32u_tl(t2, cpu_gpr[rA(ctx->opcode)]); > > #else > > tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rA(ctx->opcode)]); > > #endif > > tcg_gen_br(l4); > > gen_set_label(l3); > > #if defined(TARGET_PPC64) > > - tcg_gen_andi_tl(t2, cpu_gpr[rB(ctx->opcode)], 0x00000000FFFFFFFFULL); > > + tcg_gen_ext32u_tl(t2, cpu_gpr[rB(ctx->opcode)]); > > #else > > tcg_gen_mov_tl(cpu_gpr[rD(ctx->opcode)], cpu_gpr[rB(ctx->opcode)]); > > #endif > > Acked-by: Alexander Graf > > > Alex > > > -- Aurelien Jarno GPG: 1024D/F1BCDB73 aurelien@aurel32.net http://www.aurel32.net