[Qemu-devel] [PATCH v2 1/3] target-ppc: simplify NaN propagation for vector functions

[Qemu-devel] [PATCH v2 1/3] target-ppc: simplify NaN propagation for vector functions

[Aurelien Jarno]

Commit e024e881bb1a8b5085026589360d26ed97acdd64 provided a pickNaN()
function for PowerPC, implementing the correct NaN propagation rules.
Therefore there is no need to test the operands manually, we can rely
on the softfloat code to do that.

Cc: Alexander Graf <agraf@suse.de>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
---
 target-ppc/op_helper.c |   26 +++++++-------------------
 1 files changed, 7 insertions(+), 19 deletions(-)

Note: Unfortunately the current propagation rules implemented in 
softfloat only concerns 2 operands operations, so we have to keep
HANDLE_NAN3 for now.

diff --git a/target-ppc/op_helper.c b/target-ppc/op_helper.c
index d5db484..f2c80a3 100644
--- a/target-ppc/op_helper.c
+++ b/target-ppc/op_helper.c
@@ -2087,9 +2087,7 @@ VARITH(uwm, u32)
     {                                                                   \
         int i;                                                          \
         for (i = 0; i < ARRAY_SIZE(r->f); i++) {                        \
-            HANDLE_NAN2(r->f[i], a->f[i], b->f[i]) {                    \
-                r->f[i] = func(a->f[i], b->f[i], &env->vec_status);     \
-            }                                                           \
+            r->f[i] = func(a->f[i], b->f[i], &env->vec_status);         \
         }                                                               \
     }
 VARITHFP(addfp, float32_add)
@@ -2650,9 +2648,7 @@ void helper_vrefp (ppc_avr_t *r, ppc_avr_t *b)
 {
     int i;
     for (i = 0; i < ARRAY_SIZE(r->f); i++) {
-        HANDLE_NAN1(r->f[i], b->f[i]) {
-            r->f[i] = float32_div(float32_one, b->f[i], &env->vec_status);
-        }
+        r->f[i] = float32_div(float32_one, b->f[i], &env->vec_status);
     }
 }
 
@@ -2663,9 +2659,7 @@ void helper_vrefp (ppc_avr_t *r, ppc_avr_t *b)
         float_status s = env->vec_status;                               \
         set_float_rounding_mode(rounding, &s);                          \
         for (i = 0; i < ARRAY_SIZE(r->f); i++) {                        \
-            HANDLE_NAN1(r->f[i], b->f[i]) {                             \
-                r->f[i] = float32_round_to_int (b->f[i], &s);           \
-            }                                                           \
+            r->f[i] = float32_round_to_int (b->f[i], &s);               \
         }                                                               \
     }
 VRFI(n, float_round_nearest_even)
@@ -2693,10 +2687,8 @@ void helper_vrsqrtefp (ppc_avr_t *r, ppc_avr_t *b)
 {
     int i;
     for (i = 0; i < ARRAY_SIZE(r->f); i++) {
-        HANDLE_NAN1(r->f[i], b->f[i]) {
-            float32 t = float32_sqrt(b->f[i], &env->vec_status);
-            r->f[i] = float32_div(float32_one, t, &env->vec_status);
-        }
+        float32 t = float32_sqrt(b->f[i], &env->vec_status);
+        r->f[i] = float32_div(float32_one, t, &env->vec_status);
     }
 }
 
@@ -2710,9 +2702,7 @@ void helper_vexptefp (ppc_avr_t *r, ppc_avr_t *b)
 {
     int i;
     for (i = 0; i < ARRAY_SIZE(r->f); i++) {
-        HANDLE_NAN1(r->f[i], b->f[i]) {
-            r->f[i] = float32_exp2(b->f[i], &env->vec_status);
-        }
+        r->f[i] = float32_exp2(b->f[i], &env->vec_status);
     }
 }
 
@@ -2720,9 +2710,7 @@ void helper_vlogefp (ppc_avr_t *r, ppc_avr_t *b)
 {
     int i;
     for (i = 0; i < ARRAY_SIZE(r->f); i++) {
-        HANDLE_NAN1(r->f[i], b->f[i]) {
-            r->f[i] = float32_log2(b->f[i], &env->vec_status);
-        }
+        r->f[i] = float32_log2(b->f[i], &env->vec_status);
     }
 }
 
-- 
1.7.2.3

[Qemu-devel] [PATCH v2 2/3] target-ppc: use softfloat min/max functions

[Aurelien Jarno]

Use the new softfloat float32_min() and float32_max() to implement the
vminfp and vmaxfp instructions.

Cc: Alexander Graf <agraf@suse.de>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
---
 target-ppc/op_helper.c |   20 ++------------------
 1 files changed, 2 insertions(+), 18 deletions(-)

diff --git a/target-ppc/op_helper.c b/target-ppc/op_helper.c
index f2c80a3..f1cdef9 100644
--- a/target-ppc/op_helper.c
+++ b/target-ppc/op_helper.c
@@ -2092,6 +2092,8 @@ VARITH(uwm, u32)
     }
 VARITHFP(addfp, float32_add)
 VARITHFP(subfp, float32_sub)
+VARITHFP(minfp, float32_min)
+VARITHFP(maxfp, float32_max)
 #undef VARITHFP
 
 #define VARITHSAT_CASE(type, op, cvt, element)                          \
@@ -2369,24 +2371,6 @@ VMINMAX(uw, u32)
 #undef VMINMAX_DO
 #undef VMINMAX
 
-#define VMINMAXFP(suffix, rT, rF)                                       \
-    void helper_v##suffix (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b)    \
-    {                                                                   \
-        int i;                                                          \
-        for (i = 0; i < ARRAY_SIZE(r->f); i++) {                        \
-            HANDLE_NAN2(r->f[i], a->f[i], b->f[i]) {                    \
-                if (float32_lt_quiet(a->f[i], b->f[i], &env->vec_status)) { \
-                    r->f[i] = rT->f[i];                                 \
-                } else {                                                \
-                    r->f[i] = rF->f[i];                                 \
-                }                                                       \
-            }                                                           \
-        }                                                               \
-    }
-VMINMAXFP(minfp, a, b)
-VMINMAXFP(maxfp, b, a)
-#undef VMINMAXFP
-
 void helper_vmladduhm (ppc_avr_t *r, ppc_avr_t *a, ppc_avr_t *b, ppc_avr_t *c)
 {
     int i;
-- 
1.7.2.3

[Qemu-devel] [PATCH v2 3/3] target-ppc: remove old CONFIG_SOFTFLOAT #ifdef

[Aurelien Jarno]

target-ppc has been switched to softfloat only long ago, but a
few #ifdef CONFIG_SOFTFLOAT have been forgotten. Remove them.

Cc: Alexander Graf <agraf@suse.de>
Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
---
 target-ppc/helper.h    |    2 --
 target-ppc/op_helper.c |   11 -----------
 target-ppc/translate.c |    2 --
 3 files changed, 0 insertions(+), 15 deletions(-)

diff --git a/target-ppc/helper.h b/target-ppc/helper.h
index 7c02be9..ead0f12 100644
--- a/target-ppc/helper.h
+++ b/target-ppc/helper.h
@@ -51,9 +51,7 @@ DEF_HELPER_FLAGS_1(cntlzw32, TCG_CALL_CONST | TCG_CALL_PURE, i32, i32)
 DEF_HELPER_FLAGS_2(brinc, TCG_CALL_CONST | TCG_CALL_PURE, tl, tl, tl)
 
 DEF_HELPER_0(float_check_status, void)
-#ifdef CONFIG_SOFTFLOAT
 DEF_HELPER_0(reset_fpstatus, void)
-#endif
 DEF_HELPER_2(compute_fprf, i32, i64, i32)
 DEF_HELPER_2(store_fpscr, void, i64, i32)
 DEF_HELPER_1(fpscr_clrbit, void, i32)
diff --git a/target-ppc/op_helper.c b/target-ppc/op_helper.c
index f1cdef9..0b0cdb1 100644
--- a/target-ppc/op_helper.c
+++ b/target-ppc/op_helper.c
@@ -972,7 +972,6 @@ void helper_store_fpscr (uint64_t arg, uint32_t mask)
 
 void helper_float_check_status (void)
 {
-#ifdef CONFIG_SOFTFLOAT
     if (env->exception_index == POWERPC_EXCP_PROGRAM &&
         (env->error_code & POWERPC_EXCP_FP)) {
         /* Differred floating-point exception after target FPR update */
@@ -990,22 +989,12 @@ void helper_float_check_status (void)
             float_inexact_excp();
         }
     }
-#else
-    if (env->exception_index == POWERPC_EXCP_PROGRAM &&
-        (env->error_code & POWERPC_EXCP_FP)) {
-        /* Differred floating-point exception after target FPR update */
-        if (msr_fe0 != 0 || msr_fe1 != 0)
-            helper_raise_exception_err(env->exception_index, env->error_code);
-    }
-#endif
 }
 
-#ifdef CONFIG_SOFTFLOAT
 void helper_reset_fpstatus (void)
 {
     set_float_exception_flags(0, &env->fp_status);
 }
-#endif
 
 /* fadd - fadd. */
 uint64_t helper_fadd (uint64_t arg1, uint64_t arg2)
diff --git a/target-ppc/translate.c b/target-ppc/translate.c
index a943dbc..5659436 100644
--- a/target-ppc/translate.c
+++ b/target-ppc/translate.c
@@ -212,9 +212,7 @@ struct opc_handler_t {
 
 static inline void gen_reset_fpstatus(void)
 {
-#ifdef CONFIG_SOFTFLOAT
     gen_helper_reset_fpstatus();
-#endif
 }
 
 static inline void gen_compute_fprf(TCGv_i64 arg, int set_fprf, int set_rc)
-- 
1.7.2.3

Re: [Qemu-devel] [PATCH v2 1/3] target-ppc: simplify NaN propagation for vector functions

[Peter Maydell]

On 20 April 2011 12:32, Aurelien Jarno <aurelien@aurel32.net> wrote:
> Commit e024e881bb1a8b5085026589360d26ed97acdd64 provided a pickNaN()
> function for PowerPC, implementing the correct NaN propagation rules.
> Therefore there is no need to test the operands manually, we can rely
> on the softfloat code to do that.
>
> Cc: Alexander Graf <agraf@suse.de>
> Signed-off-by: Aurelien Jarno <aurelien@aurel32.net>
> ---
>  target-ppc/op_helper.c |   26 +++++++-------------------
>  1 files changed, 7 insertions(+), 19 deletions(-)
>
> Note: Unfortunately the current propagation rules implemented in
> softfloat only concerns 2 operands operations, so we have to keep
> HANDLE_NAN3 for now.

These first two patches remove all of the uses of HANDLE_NAN1 and
HANDLE_NAN2, so we can just delete those macro definitions, right?

You could clean up DO_HANDLE_NAN a little:

#define DO_HANDLE_NAN(result, x)               \
    if (float32_is_any_nan(x)) {               \
        result = float32_maybe_silence_nan(x); \
    } else

On a slight tangent:

I need to add ARM support for fused multiply-accumulate (vfma,vfms),
so perhaps in the long run it would be better to make them softfloat
primitives? (they are after all in the new IEEE spec, so they're in
softfloat's domain in some sense.) That would move the 'propagate one
of 3 NaNs' logic into softfloat.

(I suspect that implementing fused-mac by doing intermediate results
mas float64 will set the Inexact bit for some cases where the hardware
will not, but I haven't thought too deeply about it yet.)

-- PMM

Re: [Qemu-devel] [PATCH v2 1/3] target-ppc: simplify NaN propagation for vector functions

[Nathan Froyd]

On Wed, Apr 20, 2011 at 01:04:48PM +0100, Peter Maydell wrote:
> I need to add ARM support for fused multiply-accumulate (vfma,vfms),
> so perhaps in the long run it would be better to make them softfloat
> primitives? (they are after all in the new IEEE spec, so they're in
> softfloat's domain in some sense.) That would move the 'propagate one
> of 3 NaNs' logic into softfloat.

+1 to implementing fma in softfloat.

-Nathan