From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([140.186.70.92]:47125) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QF9Jf-0001Pe-4I for qemu-devel@nongnu.org; Wed, 27 Apr 2011 14:18:23 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1QF9Jd-0003wj-It for qemu-devel@nongnu.org; Wed, 27 Apr 2011 14:18:23 -0400 Received: from hall.aurel32.net ([88.191.126.93]:56802) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QF9Jd-0003we-E2 for qemu-devel@nongnu.org; Wed, 27 Apr 2011 14:18:21 -0400 Date: Wed, 27 Apr 2011 20:18:19 +0200 From: Aurelien Jarno Message-ID: <20110427181819.GC12989@volta.aurel32.net> References: <18082259.13471303694638277.JavaMail.weblogic@epv6ml05> MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-15 Content-Disposition: inline In-Reply-To: <18082259.13471303694638277.JavaMail.weblogic@epv6ml05> Subject: Re: [Qemu-devel] [PATCH] target-arm: fix LDMIA bug on page boundary List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: YuYeon Oh Cc: "qemu-devel@nongnu.org" On Mon, Apr 25, 2011 at 01:23:58AM +0000, YuYeon Oh wrote: > target-arm: fix LDMIA bug on page boundary > > When consecutive memory locations are on page boundary, a base register may be > loaded before page fault occurs. After page fault handling, it losts the memory > location information. To solve this problem, loading a base register has to put back. > > Signed-off-by: Yuyeon Oh > --- > target-arm/translate.c | 10 +++++++++- > 1 files changed, 9 insertions(+), 1 deletions(-) Thanks, applied. > diff --git a/target-arm/translate.c b/target-arm/translate.c > index e1bda57..410e7c4 100644 > --- a/target-arm/translate.c > +++ b/target-arm/translate.c > @@ -7967,7 +7967,8 @@ static int disas_thumb2_insn(CPUState *env, DisasContext *s, uint16_t insn_hw1) > } > } > } else { > - int i; > + int i, loaded_base = 0; > + TCGv loaded_var; > /* Load/store multiple. */ > addr = load_reg(s, rn); > offset = 0; > @@ -7979,6 +7980,7 @@ static int disas_thumb2_insn(CPUState *env, DisasContext *s, uint16_t insn_hw1) > tcg_gen_addi_i32(addr, addr, -offset); > } > > + TCGV_UNUSED(loaded_var); > for (i = 0; i < 16; i++) { > if ((insn & (1 << i)) == 0) > continue; > @@ -7987,6 +7989,9 @@ static int disas_thumb2_insn(CPUState *env, DisasContext *s, uint16_t insn_hw1) > tmp = gen_ld32(addr, IS_USER(s)); > if (i == 15) { > gen_bx(s, tmp); > + } else if (i == rn) { > + loaded_var = tmp; > + loaded_base = 1; > } else { > store_reg(s, i, tmp); > } > @@ -7997,6 +8002,9 @@ static int disas_thumb2_insn(CPUState *env, DisasContext *s, uint16_t insn_hw1) > } > tcg_gen_addi_i32(addr, addr, 4); > } > + if (loaded_base) { > + store_reg(s, rn, loaded_var); > + } > if (insn & (1 << 21)) { > /* Base register writeback. */ > if (insn & (1 << 24)) { > -- > 1.7.4.msysgit.0 -- Aurelien Jarno GPG: 1024D/F1BCDB73 aurelien@aurel32.net http://www.aurel32.net