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From: Paul Brook <paul@codesourcery.com>
To: qemu-devel@nongnu.org
Cc: Blue Swirl <blauwirbel@gmail.com>, Richard Henderson <rth@twiddle.net>
Subject: Re: [Qemu-devel] TCG: AREG0 removal planning
Date: Tue, 10 May 2011 23:57:17 +0100	[thread overview]
Message-ID: <201105102357.17637.paul@codesourcery.com> (raw)
In-Reply-To: <4DC9B51B.20505@twiddle.net>

> While we're at it, let us change things a bit further to allow guest
> byte-swap load/store insns to be implemented more efficiently.  For
> instance, currently a sparc load_asr (little-endian), as emulated on
> an x86 host, does the byte swap twice.

FWIW this also ends up interacting with the device and bus models. This is 
partially implemented by the endian parameter of cpu_register_io_memory et. 
al.  This may also be a runtime property, either part of the CPU state (e.g. 
ARM where instruction and data accesses may have different endianness), or 
even a per-page TLB attribute (PPC?).

Paul

  reply	other threads:[~2011-05-10 22:57 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2011-05-10 20:54 [Qemu-devel] TCG: AREG0 removal planning Blue Swirl
2011-05-10 21:28 ` Paul Brook
2011-05-11 17:25   ` Blue Swirl
2011-05-11 18:39     ` Lluís
2011-05-11 19:15       ` Blue Swirl
2011-05-12 15:02     ` Avi Kivity
2011-05-16 16:16     ` Paul Brook
2011-05-16 19:18       ` Blue Swirl
2011-05-10 21:31 ` Stefan Weil
2011-05-10 21:58 ` Richard Henderson
2011-05-10 22:57   ` Paul Brook [this message]
2011-05-11 17:35     ` Blue Swirl
2011-05-11 17:32   ` Blue Swirl

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