From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([140.186.70.92]:45183) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QJvrm-0001jG-TF for qemu-devel@nongnu.org; Tue, 10 May 2011 18:57:27 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1QJvrl-0003tI-T6 for qemu-devel@nongnu.org; Tue, 10 May 2011 18:57:22 -0400 Received: from mail.codesourcery.com ([38.113.113.100]:34643) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QJvrl-0003ss-Kp for qemu-devel@nongnu.org; Tue, 10 May 2011 18:57:21 -0400 From: Paul Brook Date: Tue, 10 May 2011 23:57:17 +0100 References: <4DC9B51B.20505@twiddle.net> In-Reply-To: <4DC9B51B.20505@twiddle.net> MIME-Version: 1.0 Content-Type: Text/Plain; charset="utf-8" Content-Transfer-Encoding: 7bit Message-Id: <201105102357.17637.paul@codesourcery.com> Subject: Re: [Qemu-devel] TCG: AREG0 removal planning List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org Cc: Blue Swirl , Richard Henderson > While we're at it, let us change things a bit further to allow guest > byte-swap load/store insns to be implemented more efficiently. For > instance, currently a sparc load_asr (little-endian), as emulated on > an x86 host, does the byte swap twice. FWIW this also ends up interacting with the device and bus models. This is partially implemented by the endian parameter of cpu_register_io_memory et. al. This may also be a runtime property, either part of the CPU state (e.g. ARM where instruction and data accesses may have different endianness), or even a per-page TLB attribute (PPC?). Paul