From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([140.186.70.92]:49699) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QLGl1-0005RW-PU for qemu-devel@nongnu.org; Sat, 14 May 2011 11:27:56 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1QLGl0-00014D-6n for qemu-devel@nongnu.org; Sat, 14 May 2011 11:27:55 -0400 Received: from mail-bw0-f45.google.com ([209.85.214.45]:34114) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QLGl0-00013u-0Q for qemu-devel@nongnu.org; Sat, 14 May 2011 11:27:54 -0400 Received: by bwz16 with SMTP id 16so3071697bwz.4 for ; Sat, 14 May 2011 08:27:52 -0700 (PDT) Sender: Eduard - Gabriel Munteanu Date: Sat, 14 May 2011 18:27:46 +0300 From: Eduard - Gabriel Munteanu Message-ID: <20110514152746.GA2951@localhost> References: <20110421070347.GG11968@yookeroo> <20110421184730.GA7117@localhost> <20110510014426.GA12722@yookeroo.fritz.box> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20110510014426.GA12722@yookeroo.fritz.box> Subject: Re: [Qemu-devel] Supporting emulation of IOMMUs List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org, Joerg.Rodel@amd.com, benh@kernel.crashing.org, aik@ozlabs.ru, agraf@suse.de, Anthony Liguori On Tue, May 10, 2011 at 11:44:26AM +1000, David Gibson wrote: > On Thu, Apr 21, 2011 at 09:47:31PM +0300, Eduard - Gabriel Munteanu wrote: > > On Thu, Apr 21, 2011 at 05:03:47PM +1000, David Gibson wrote: > > > A few months ago, Eduard - Gabriel Munteanu posted a series of patches > > > implementing support for emulating the AMD PCI IOMMU > > > (http://lists.nongnu.org/archive/html/qemu-devel/2011-01/msg03196.html). > > > > > > In fact, this series implemented a general DMA/IOMMU layer which can > > > be used by any device model, and one translation backend for this > > > implementing the AMD specific PCI IOMMU. > > > > > > These patches don't seem to have gone anywhere for the last few > > > months, however, and so far I've been unable to contact the author > > > (trying again with this mail). > > > > > > I have an interest in this code, because the pSeries machine will also > > > need IOMMU emulation support. At present we only support virtual > > > devices, through the PAPR interface, and we have support for the > > > hypervisor-controller IOMMU translation in the PAPR VIO code. > > > However, we want to add PCI device support and this will also need > > > IOMMU translation. > > > > > > The series seems to have the right basic approach, so if the author is > > > indeed MIA, I was planning to pick up the patches and resubmit them > > > (with support for the pSeries IOMMU added). > > > > Hi, > > > > Not really MIA, but I've been a bit busy lately, so I'm sorry if I > > couldn't answer your mail in a timely fashion. > > > > I'll try making another merge attempt tonight/tomorrow. > > Ok. Did this happen? Sorry, I've been away the last couple of weeks > - I had a google at the qemu-devel archives but couldn't spot a new > merge, but did I just not look hard enough? [snip] No, I've made some progress but I've still got a few concerns to address, mainly how to handle unaligned accesses and some things related to the IOMMU behavior like target aborts. I've added some macro magic to declare bus-specific interfaces and converted PCI devices to use pci_memory_*(). I'll try not to hold this back too much, but I can't make promises wrt timing. Eduard