Re: [Qemu-devel] [PATCH 00/26] q35 chipset support for native pci express support

[Isaku Yamahata <yamahata@valinux.co.jp>]

On Tue, May 17, 2011 at 04:21:11PM +0200, Jan Kiszka wrote:
> I also succeeded with passing through a PCIe host device. Nicely, the
> full set capabilities showed up on the guest side this way. But GPU
> pass-through did not improve this way (it rather regressed, yet unclear
> why).

Interesting.

> > I had a quick look at your patches.
> > With seabios patch of 94710189f5323034e00b510fe5a0865a7b576a9f,
> > you ignored MCFG area.
> > 
> > (start = Q35_HOST_BRIDGE_PCIEXBAR_ADDR, size = 256MB) is used
> > for MCFG (!= pci region), so it can't be used for PCI region.
> > That's why 256M is added to s.
> > And Q35_HOST_BRIDGE_PCIEXBAR_ADDR in dev-q35.h also needs to be adjusted.
> 
> Confused. Where was the PCI region located without my hack?

I mean the following patch on top of your tree.
At the moment, I only compiled it.

diff --git a/src/dev-q35.c b/src/dev-q35.c
index c0aa057..eee50c4 100644
--- a/src/dev-q35.c
+++ b/src/dev-q35.c
@@ -36,13 +36,15 @@ void mch_mem_addr_init(u16 bdf, void *arg)
 
     /*
      * BUILD_MAX_HIGHMEM == 0xc0000000
-     * [0xc000 0000, 0xf000 0000) for MCFG
-     *  4GB - 1GB, 4GB - 256MB
+     * [0xc000 0000, 0xd000 0000) for MCFG
+     *  3GB ,        3GB + 256MB
+     * [0xd000 0000, 0xf000 0000) for pci memory region
+     *  3GB + 256MB, 4GB - 256MB
      * [0xf000 0000, 0xfec0 0000) for DMI interface(subtractive decode)
      *  4GB - 256MB, 4GB - 20MB
      */
-    s = BUILD_MAX_HIGHMEM;
-    e = s + 128 * 1024 * 1024 - 1 + 512 * 1024 * 1024;
+    s = Q35_HOST_BRIDGE_PCIEXBAR_ADDR + Q35_HOST_BRIDGE_PCIEXBAR_SIZE;
+    e = s + 512 * 1024 * 1024 - 1;
     pci_region_init(addr->pci_bios_mem_region, s, e);
 
     /* pci_bios_mem_addr + <some value: 128M is used here> */
diff --git a/src/dev-q35.h b/src/dev-q35.h
index f5cae62..0d83dba 100644
--- a/src/dev-q35.h
+++ b/src/dev-q35.h
@@ -8,7 +8,7 @@
 #define  Q35_HOST_BRIDGE_SMRAM          0x9d
 #define Q35_HOST_BRIDGE_PCIEXBAR        0x60
 #define  Q35_HOST_BRIDGE_PCIEXBAR_SIZE  (256 * 1024 * 1024)
-#define  Q35_HOST_BRIDGE_PCIEXBAR_ADDR  0xe0000000
+#define  Q35_HOST_BRIDGE_PCIEXBAR_ADDR   BUILD_MAX_HIGHMEM
 #define  Q35_HOST_BRIDGE_PCIEXBAREN     ((u64)1)
 #define  Q35_HOST_PCIE_PCI_SEGMENT      0
 #define  Q35_HOST_PCIE_START_BUS_NUMBER 0


> BTW, the PCI bar mapping failures of VGA or e1000 are independent of
> that seabios commit. You should see them with your tree as well.

Hmm, I'll look into it.


> > After pushing out pci id clean up and once they are accepted,
> > I'll publish rebased/cleaned up one.
> 
> Note that I dropped "simply i440fx initialization". It was a premature
> cleanup that caused regressions. The good news: I'm working on PAM/SMRAM
> fixes that will include such a cleanup after removing the need for the
> init function. The bad news: Those patches will force you to rebase
> again (to break out the new PAM/SMRAM code).

Please keep CCed on me.
-- 
yamahata