From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([140.186.70.92]:34773) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QPdDn-0002Gm-Jl for qemu-devel@nongnu.org; Thu, 26 May 2011 12:15:40 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1QPdDl-00078O-AR for qemu-devel@nongnu.org; Thu, 26 May 2011 12:15:39 -0400 Received: from adelie.canonical.com ([91.189.90.139]:40041) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QPdDl-000781-6I for qemu-devel@nongnu.org; Thu, 26 May 2011 12:15:37 -0400 Received: from loganberry.canonical.com ([91.189.90.37]) by adelie.canonical.com with esmtp (Exim 4.71 #1 (Debian)) id 1QPdDk-0001yb-B8 for ; Thu, 26 May 2011 16:15:36 +0000 Received: from loganberry.canonical.com (localhost [127.0.0.1]) by loganberry.canonical.com (Postfix) with ESMTP id 4E2832E814B for ; Thu, 26 May 2011 16:15:36 +0000 (UTC) MIME-Version: 1.0 Content-Type: text/plain; charset="utf-8" Content-Transfer-Encoding: quoted-printable Date: Thu, 26 May 2011 16:09:30 -0000 From: Nathan Whitehorn <788697@bugs.launchpad.net> Sender: bounces@canonical.com References: <20110526160930.15535.57397.malonedeb@soybean.canonical.com> Message-Id: <20110526160931.15535.77446.malone@soybean.canonical.com> Errors-To: bounces@canonical.com Subject: [Qemu-devel] [Bug 788697] Re: [PowerPC] [patch] mtmsr does not preserve high bits of MSR Reply-To: Bug 788697 <788697@bugs.launchpad.net> List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org ** Patch added: "mtmstr.diff" https://bugs.launchpad.net/bugs/788697/+attachment/2143748/+files/mtmstr= .diff -- = You received this bug notification because you are a member of qemu- devel-ml, which is subscribed to QEMU. https://bugs.launchpad.net/bugs/788697 Title: [PowerPC] [patch] mtmsr does not preserve high bits of MSR Status in QEMU: New Bug description: The mtmsr instruction on 64-bit PPC does not preserve the high-order 32-bits of the MSR the way it is supposed to, instead setting them to 0, which takes 64-bit code out of 64-bit mode. There is some code that does the right thing, but it brokenly only preserves these bits when the thread is not in 64-bit mode (i.e. when it doesn't matter). The attached patch unconditionally enables this code when TARGET_PPC64 is set, per the ISA spec, which fixes early boot failures trying to start FreeBSD/powerpc64 under qemu.