From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([140.186.70.92]:45971) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QRnS2-0001ve-QU for qemu-devel@nongnu.org; Wed, 01 Jun 2011 11:35:20 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1QRnS0-00044P-Kv for qemu-devel@nongnu.org; Wed, 01 Jun 2011 11:35:18 -0400 Received: from mail-bw0-f45.google.com ([209.85.214.45]:55471) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1QRnRz-000449-Uh for qemu-devel@nongnu.org; Wed, 01 Jun 2011 11:35:16 -0400 Received: by bwz16 with SMTP id 16so189032bwz.4 for ; Wed, 01 Jun 2011 08:35:14 -0700 (PDT) Sender: Eduard - Gabriel Munteanu Date: Wed, 1 Jun 2011 18:35:10 +0300 From: Eduard - Gabriel Munteanu Message-ID: <20110601153510.GA3339@localhost> References: <1306892315-7306-1-git-send-email-eduard.munteanu@linux360.ro> <1306892315-7306-2-git-send-email-eduard.munteanu@linux360.ro> <4DE64646.3010505@twiddle.net> <20110601145227.GA2936@localhost> <4DE65629.1010300@twiddle.net> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <4DE65629.1010300@twiddle.net> Subject: Re: [Qemu-devel] [RFC PATCH 01/13] Generic DMA memory access interface List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Richard Henderson Cc: aliguori@us.ibm.com, kvm@vger.kernel.org, mst@redhat.com, aik@ozlabs.ru, joro@8bytes.org, seabios@seabios.org, qemu-devel@nongnu.org, agraf@suse.de, blauwirbel@gmail.com, yamahata@valinux.co.jp, paul@codesourcery.com, kevin@koconnor.net, avi@redhat.com, dwg@au1.ibm.com, david@gibson.dropbear.id.au On Wed, Jun 01, 2011 at 08:09:29AM -0700, Richard Henderson wrote: > On 06/01/2011 07:52 AM, Eduard - Gabriel Munteanu wrote: > > The main selling point is there are more chances to screw up if every > > bus layer implements these manually. And it's really convenient, > > especially if we get to add another ld/st. > > If we drop the ld/st, we're talking about 5 lines for every bus layer. > > If I recall, there was just the one driver that actually uses the ld/st > interface; most used the read/write interface. Hm, indeed there seem to be far fewer uses of those now, actually my patches don't seem to be using those. What do you guys think? Will these go away completely? > > If I understand correctly you need some sort of shared state between > > IOMMUs or units residing on different buses. Then you should be able to > > get to it even with this API, just like I do with my AMD IOMMU state by > > upcasting. It doesn't seem to matter whether you've got an opaque, that > > opaque could very well be reachable by upcasting. > > > > Did I get this wrong? > > Can you honestly tell me that > > > +static int amd_iommu_translate(DMADevice *dev, > > + dma_addr_t addr, > > + dma_addr_t *paddr, > > + dma_addr_t *len, > > + int is_write) > > +{ > > + PCIDevice *pci_dev = container_of(dev, PCIDevice, dma); > > + PCIDevice *iommu_dev = DO_UPCAST(PCIDevice, qdev, dev->mmu->iommu); > > + AMDIOMMUState *s = DO_UPCAST(AMDIOMMUState, dev, iommu_dev); > > THREE (3) upcasts is a sane to write maintainable software? > The margin for error here is absolutely enormous. > > If you had just passed in that AMDIOMMUState* as the opaque > value, it would be trivial to look at the initialization > statement and the callback function to verify that the right > value is being passed. Maybe it's not nice, but you're missing the fact upcasting gives you some type safety. With opaques you have none. Plus you also get the PCI device that made the call while you're at it. Eduard > r~