qemu-devel.nongnu.org archive mirror
 help / color / mirror / Atom feed
From: "Michael S. Tsirkin" <mst@redhat.com>
To: Jan Kiszka <jan.kiszka@siemens.com>
Cc: qemu-devel <qemu-devel@nongnu.org>
Subject: Re: [Qemu-devel] [PATCH v2 8/9] msix: Align MSI-X constants to libpci definitions and extend them
Date: Wed, 8 Jun 2011 22:46:31 +0300	[thread overview]
Message-ID: <20110608194631.GB30805@redhat.com> (raw)
In-Reply-To: <219d3206ad6eafed76d4f108a40912fe72884e19.1307550106.git.jan.kiszka@siemens.com>

On Wed, Jun 08, 2011 at 06:21:51PM +0200, Jan Kiszka wrote:
> Add PCI_MSIX_TABLE and PCI_MSIX_PBA, align other MSIX related constant
> names to libpci style. Will be used for device assignment code in
> qemu-kvm.
> 
> Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
> ---
>  hw/msix.c     |   24 +++++++++++-------------
>  hw/pci_regs.h |   14 ++++++++------
>  2 files changed, 19 insertions(+), 19 deletions(-)
> 
> diff --git a/hw/msix.c b/hw/msix.c
> index 600f5fb..b20cf7c 100644
> --- a/hw/msix.c
> +++ b/hw/msix.c
> @@ -16,15 +16,12 @@
>  #include "pci.h"
>  #include "range.h"
>  
> -/* MSI-X capability structure */
> -#define MSIX_TABLE_OFFSET 4
> -#define MSIX_PBA_OFFSET 8
>  #define MSIX_CAP_LENGTH 12
>  
> -/* MSI enable bit and maskall bit are in byte 1 in FLAGS register */
> -#define MSIX_CONTROL_OFFSET (PCI_MSIX_FLAGS + 1)
> -#define MSIX_ENABLE_MASK (PCI_MSIX_FLAGS_ENABLE >> 8)
> -#define MSIX_MASKALL_MASK (PCI_MSIX_FLAGS_MASKALL >> 8)
> +/* MSI enable bit and maskall bit are in byte 1 in control register */
> +#define MSIX_CONTROL_OFFSET (PCI_MSIX_CTRL + 1)
> +#define MSIX_ENABLE_MASK (PCI_MSIX_ENABLE >> 8)
> +#define MSIX_MASKALL_MASK (PCI_MSIX_MASK >> 8)
>  
>  /* MSI-X table format */
>  #define MSIX_MSG_ADDR 0
> @@ -58,8 +55,9 @@ static int msix_add_config(struct PCIDevice *pdev, unsigned short nentries,
>      uint8_t *config;
>      uint32_t new_size;
>  
> -    if (nentries < 1 || nentries > PCI_MSIX_FLAGS_QSIZE + 1)
> +    if (nentries < 1 || nentries > PCI_MSIX_TABSIZE + 1) {
>          return -EINVAL;
> +    }
>      if (bar_size > 0x80000000)
>          return -ENOSPC;
>  
> @@ -80,11 +78,11 @@ static int msix_add_config(struct PCIDevice *pdev, unsigned short nentries,
>          return config_offset;
>      config = pdev->config + config_offset;
>  
> -    pci_set_word(config + PCI_MSIX_FLAGS, nentries - 1);
> +    pci_set_word(config + PCI_MSIX_CTRL, nentries - 1);
>      /* Table on top of BAR */
> -    pci_set_long(config + MSIX_TABLE_OFFSET, bar_size | bar_nr);
> +    pci_set_long(config + PCI_MSIX_TABLE, bar_size | bar_nr);
>      /* Pending bits on top of that */
> -    pci_set_long(config + MSIX_PBA_OFFSET, (bar_size + MSIX_PAGE_PENDING) |
> +    pci_set_long(config + PCI_MSIX_PBA, (bar_size + MSIX_PAGE_PENDING) |
>                   bar_nr);
>      pdev->msix_cap = config_offset;
>      /* Make flags bit writable. */
> @@ -208,11 +206,11 @@ void msix_mmio_map(PCIDevice *d, int region_num,
>                     pcibus_t addr, pcibus_t size, int type)
>  {
>      uint8_t *config = d->config + d->msix_cap;
> -    uint32_t table = pci_get_long(config + MSIX_TABLE_OFFSET);
> +    uint32_t table = pci_get_long(config + PCI_MSIX_TABLE);
>      uint32_t offset = table & ~(MSIX_PAGE_SIZE - 1);
>      /* TODO: for assigned devices, we'll want to make it possible to map
>       * pending bits separately in case they are in a separate bar. */
> -    int table_bir = table & PCI_MSIX_FLAGS_BIRMASK;
> +    int table_bir = table & PCI_MSIX_BIR;
>  
>      if (table_bir != region_num)
>          return;
> diff --git a/hw/pci_regs.h b/hw/pci_regs.h
> index 5a5ab89..c17c22f 100644
> --- a/hw/pci_regs.h
> +++ b/hw/pci_regs.h
> @@ -300,12 +300,14 @@
>  #define PCI_MSI_DATA_64		12	/* 16 bits of data for 64-bit devices */
>  #define PCI_MSI_MASK_64		16	/* Mask bits register for 64-bit devices */
>  
> -/* MSI-X registers (these are at offset PCI_MSIX_FLAGS) */
> -#define PCI_MSIX_FLAGS		2
> -#define  PCI_MSIX_FLAGS_QSIZE	0x7FF
> -#define  PCI_MSIX_FLAGS_ENABLE	(1 << 15)
> -#define  PCI_MSIX_FLAGS_MASKALL	(1 << 14)
> -#define PCI_MSIX_FLAGS_BIRMASK	(7 << 0)
> +/* MSI-X registers */
> +#define PCI_MSIX_CTRL           2       /* Message control */
> +#define  PCI_MSIX_TABSIZE       0x7FF   /* Table size - 1 */
> +#define  PCI_MSIX_MASK          0x4000  /* Mask all vectors */
> +#define  PCI_MSIX_ENABLE        0x8000  /* Enable MSI-X */
> +#define PCI_MSIX_TABLE          4       /* MSI-X table */
> +#define PCI_MSIX_PBA            8       /* Pending bit array */
> +#define  PCI_MSIX_BIR           0x7     /* BAR indication register */
>  
>  /* CompactPCI Hotswap Register */

We are using pci_regs.h from Linux, not libpci, as the base.
What I see there is:

#define PCI_MSIX_FLAGS          2
#define  PCI_MSIX_FLAGS_QSIZE   0x7FF
#define  PCI_MSIX_FLAGS_ENABLE  (1 << 15)
#define  PCI_MSIX_FLAGS_MASKALL (1 << 14)
#define PCI_MSIX_TABLE          4
#define PCI_MSIX_PBA            8
#define  PCI_MSIX_FLAGS_BIRMASK (7 << 0)
#define PCI_MSIX_ENTRY_SIZE             16
#define  PCI_MSIX_ENTRY_LOWER_ADDR      0
#define  PCI_MSIX_ENTRY_UPPER_ADDR      4
#define  PCI_MSIX_ENTRY_DATA            8
#define  PCI_MSIX_ENTRY_VECTOR_CTRL     12
#define   PCI_MSIX_ENTRY_CTRL_MASKBIT   1


Let's stick to that please.

>  
> -- 
> 1.7.1

  reply	other threads:[~2011-06-08 19:46 UTC|newest]

Thread overview: 30+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2011-06-08 16:21 [Qemu-devel] [PATCH v2 0/9] msi: Small cleanups and fixes Jan Kiszka
2011-06-08 16:21 ` [Qemu-devel] [PATCH v2 1/9] msi: Fix copy&paste mistake in msi_uninit Jan Kiszka
2011-06-08 16:21 ` [Qemu-devel] [PATCH v2 2/9] msi: Guard msi/msix_write_config with msi_present Jan Kiszka
2011-06-08 16:21 ` [Qemu-devel] [PATCH v2 3/9] msi: Guard msi_reset " Jan Kiszka
2011-06-08 16:21 ` [Qemu-devel] [PATCH v2 4/9] msi: Use msi/msix_present more consistently Jan Kiszka
2011-06-08 16:21 ` [Qemu-devel] [PATCH v2 5/9] msi: Invoke msi/msix_reset from PCI core Jan Kiszka
2011-06-08 19:59   ` Michael S. Tsirkin
2011-06-08 20:47     ` Jan Kiszka
2011-06-08 16:21 ` [Qemu-devel] [PATCH v2 6/9] msi: Invoke msi/msix_write_config " Jan Kiszka
2011-06-08 16:21 ` [Qemu-devel] [PATCH v2 7/9] msi: Invoke msi/msix_uninit " Jan Kiszka
2011-06-08 16:21 ` [Qemu-devel] [PATCH v2 8/9] msix: Align MSI-X constants to libpci definitions and extend them Jan Kiszka
2011-06-08 19:46   ` Michael S. Tsirkin [this message]
2011-06-08 19:53   ` Michael S. Tsirkin
2011-06-08 20:48     ` Jan Kiszka
2011-06-08 21:00       ` Michael S. Tsirkin
2011-06-08 21:02         ` Jan Kiszka
2011-06-08 21:09           ` Michael S. Tsirkin
2011-06-08 21:11             ` Jan Kiszka
2011-06-08 21:15               ` Michael S. Tsirkin
2011-06-08 16:21 ` [Qemu-devel] [PATCH v2 9/9] msi: Move PCI_MSI_PENDING_32/64 into pci_regs.h Jan Kiszka
2011-06-08 19:48   ` Michael S. Tsirkin
2011-06-08 20:44     ` Jan Kiszka
2011-06-08 20:56       ` Michael S. Tsirkin
2011-06-08 20:57         ` Jan Kiszka
2011-06-08 21:01           ` Michael S. Tsirkin
2011-06-08 21:03             ` Jan Kiszka
2011-06-08 21:14               ` Michael S. Tsirkin
2011-06-08 21:18                 ` Jan Kiszka
2011-06-08 21:24                   ` Jan Kiszka
2011-06-08 21:30                   ` Michael S. Tsirkin

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20110608194631.GB30805@redhat.com \
    --to=mst@redhat.com \
    --cc=jan.kiszka@siemens.com \
    --cc=qemu-devel@nongnu.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).