From: Isaku Yamahata <yamahata@valinux.co.jp>
To: Jan Kiszka <jan.kiszka@web.de>
Cc: qemu-devel <qemu-devel@nongnu.org>,
"Michael S. Tsirkin" <mst@redhat.com>
Subject: Re: [Qemu-devel] [PATCH] pci: Update pci_regs header
Date: Thu, 9 Jun 2011 19:36:45 +0900 [thread overview]
Message-ID: <20110609103645.GB32149@valinux.co.jp> (raw)
In-Reply-To: <4DF073C6.4000902@web.de>
pcie_aer.c change looks good.
Thanks.
On Thu, Jun 09, 2011 at 09:18:30AM +0200, Jan Kiszka wrote:
> From: Jan Kiszka <jan.kiszka@siemens.com>
>
> Pulls in latest version from kernel 3.0-rc2.
>
> Some changes around AER now require local defines as QEMU accesses the
> error source identification register via sub-words.
>
> CC: Isaku Yamahata <yamahata@valinux.co.jp>
> Signed-off-by: Jan Kiszka <jan.kiszka@siemens.com>
> ---
>
> I don't think the #define requirements of pcie_aer are upstream
> compatible, therefore private constants.
>
> This will allow to drop libpci build dependency from qemu-kvm.
>
> hw/pci_regs.h | 60 ++++++++++++++++++++++++++++++++++++++++++++++++++++----
> hw/pcie_aer.c | 9 ++++++-
> 2 files changed, 62 insertions(+), 7 deletions(-)
>
> diff --git a/hw/pci_regs.h b/hw/pci_regs.h
> index 5a5ab89..e884096 100644
> --- a/hw/pci_regs.h
> +++ b/hw/pci_regs.h
> @@ -300,12 +300,22 @@
> #define PCI_MSI_DATA_64 12 /* 16 bits of data for 64-bit devices */
> #define PCI_MSI_MASK_64 16 /* Mask bits register for 64-bit devices */
>
> -/* MSI-X registers (these are at offset PCI_MSIX_FLAGS) */
> +/* MSI-X registers */
> #define PCI_MSIX_FLAGS 2
> #define PCI_MSIX_FLAGS_QSIZE 0x7FF
> #define PCI_MSIX_FLAGS_ENABLE (1 << 15)
> #define PCI_MSIX_FLAGS_MASKALL (1 << 14)
> -#define PCI_MSIX_FLAGS_BIRMASK (7 << 0)
> +#define PCI_MSIX_TABLE 4
> +#define PCI_MSIX_PBA 8
> +#define PCI_MSIX_FLAGS_BIRMASK (7 << 0)
> +
> +/* MSI-X entry's format */
> +#define PCI_MSIX_ENTRY_SIZE 16
> +#define PCI_MSIX_ENTRY_LOWER_ADDR 0
> +#define PCI_MSIX_ENTRY_UPPER_ADDR 4
> +#define PCI_MSIX_ENTRY_DATA 8
> +#define PCI_MSIX_ENTRY_VECTOR_CTRL 12
> +#define PCI_MSIX_ENTRY_CTRL_MASKBIT 1
>
> /* CompactPCI Hotswap Register */
>
> @@ -365,6 +375,11 @@
> #define PCI_X_STATUS_266MHZ 0x40000000 /* 266 MHz capable */
> #define PCI_X_STATUS_533MHZ 0x80000000 /* 533 MHz capable */
>
> +/* PCI Bridge Subsystem ID registers */
> +
> +#define PCI_SSVID_VENDOR_ID 4 /* PCI-Bridge subsystem vendor id register */
> +#define PCI_SSVID_DEVICE_ID 6 /* PCI-Bridge subsystem device id register */
> +
> /* PCI Express capability registers */
>
> #define PCI_EXP_FLAGS 2 /* Capabilities register */
> @@ -420,7 +435,7 @@
> #define PCI_EXP_LNKCAP_L0SEL 0x00007000 /* L0s Exit Latency */
> #define PCI_EXP_LNKCAP_L1EL 0x00038000 /* L1 Exit Latency */
> #define PCI_EXP_LNKCAP_CLKPM 0x00040000 /* L1 Clock Power Management */
> -#define PCI_EXP_LNKCAP_SDERC 0x00080000 /* Suprise Down Error Reporting Capable */
> +#define PCI_EXP_LNKCAP_SDERC 0x00080000 /* Surprise Down Error Reporting Capable */
> #define PCI_EXP_LNKCAP_DLLLARC 0x00100000 /* Data Link Layer Link Active Reporting Capable */
> #define PCI_EXP_LNKCAP_LBNC 0x00200000 /* Link Bandwidth Notification Capability */
> #define PCI_EXP_LNKCAP_PN 0xff000000 /* Port Number */
> @@ -437,7 +452,10 @@
> #define PCI_EXP_LNKCTL_LABIE 0x0800 /* Lnk Autonomous Bandwidth Interrupt Enable */
> #define PCI_EXP_LNKSTA 18 /* Link Status */
> #define PCI_EXP_LNKSTA_CLS 0x000f /* Current Link Speed */
> +#define PCI_EXP_LNKSTA_CLS_2_5GB 0x01 /* Current Link Speed 2.5GT/s */
> +#define PCI_EXP_LNKSTA_CLS_5_0GB 0x02 /* Current Link Speed 5.0GT/s */
> #define PCI_EXP_LNKSTA_NLW 0x03f0 /* Nogotiated Link Width */
> +#define PCI_EXP_LNKSTA_NLW_SHIFT 4 /* start of NLW mask in link status */
> #define PCI_EXP_LNKSTA_LT 0x0800 /* Link Training */
> #define PCI_EXP_LNKSTA_SLC 0x1000 /* Slot Clock Configuration */
> #define PCI_EXP_LNKSTA_DLLLA 0x2000 /* Data Link Layer Link Active */
> @@ -486,10 +504,22 @@
> #define PCI_EXP_RTCTL_CRSSVE 0x10 /* CRS Software Visibility Enable */
> #define PCI_EXP_RTCAP 30 /* Root Capabilities */
> #define PCI_EXP_RTSTA 32 /* Root Status */
> +#define PCI_EXP_RTSTA_PME 0x10000 /* PME status */
> +#define PCI_EXP_RTSTA_PENDING 0x20000 /* PME pending */
> #define PCI_EXP_DEVCAP2 36 /* Device Capabilities 2 */
> #define PCI_EXP_DEVCAP2_ARI 0x20 /* Alternative Routing-ID */
> +#define PCI_EXP_DEVCAP2_LTR 0x800 /* Latency tolerance reporting */
> +#define PCI_EXP_OBFF_MASK 0xc0000 /* OBFF support mechanism */
> +#define PCI_EXP_OBFF_MSG 0x40000 /* New message signaling */
> +#define PCI_EXP_OBFF_WAKE 0x80000 /* Re-use WAKE# for OBFF */
> #define PCI_EXP_DEVCTL2 40 /* Device Control 2 */
> #define PCI_EXP_DEVCTL2_ARI 0x20 /* Alternative Routing-ID */
> +#define PCI_EXP_IDO_REQ_EN 0x100 /* ID-based ordering request enable */
> +#define PCI_EXP_IDO_CMP_EN 0x200 /* ID-based ordering completion enable */
> +#define PCI_EXP_LTR_EN 0x400 /* Latency tolerance reporting */
> +#define PCI_EXP_OBFF_MSGA_EN 0x2000 /* OBFF enable with Message type A */
> +#define PCI_EXP_OBFF_MSGB_EN 0x4000 /* OBFF enable with Message type B */
> +#define PCI_EXP_OBFF_WAKE_EN 0x6000 /* OBFF using WAKE# signaling */
> #define PCI_EXP_LNKCTL2 48 /* Link Control 2 */
> #define PCI_EXP_SLTCTL2 56 /* Slot Control 2 */
>
> @@ -502,9 +532,12 @@
> #define PCI_EXT_CAP_ID_VC 2
> #define PCI_EXT_CAP_ID_DSN 3
> #define PCI_EXT_CAP_ID_PWR 4
> +#define PCI_EXT_CAP_ID_VNDR 11
> +#define PCI_EXT_CAP_ID_ACS 13
> #define PCI_EXT_CAP_ID_ARI 14
> #define PCI_EXT_CAP_ID_ATS 15
> #define PCI_EXT_CAP_ID_SRIOV 16
> +#define PCI_EXT_CAP_ID_LTR 24
>
> /* Advanced Error Reporting */
> #define PCI_ERR_UNCOR_STATUS 4 /* Uncorrectable Error Status */
> @@ -556,8 +589,7 @@
> #define PCI_ERR_ROOT_FIRST_FATAL 0x00000010 /* First Fatal */
> #define PCI_ERR_ROOT_NONFATAL_RCV 0x00000020 /* Non-Fatal Received */
> #define PCI_ERR_ROOT_FATAL_RCV 0x00000040 /* Fatal Received */
> -#define PCI_ERR_ROOT_COR_SRC 52
> -#define PCI_ERR_ROOT_SRC 54
> +#define PCI_ERR_ROOT_ERR_SRC 52 /* Error Source Identification */
>
> /* Virtual Channel */
> #define PCI_VC_PORT_REG1 4
> @@ -662,4 +694,22 @@
> #define PCI_SRIOV_VFM_MO 0x2 /* Active.MigrateOut */
> #define PCI_SRIOV_VFM_AV 0x3 /* Active.Available */
>
> +#define PCI_LTR_MAX_SNOOP_LAT 0x4
> +#define PCI_LTR_MAX_NOSNOOP_LAT 0x6
> +#define PCI_LTR_VALUE_MASK 0x000003ff
> +#define PCI_LTR_SCALE_MASK 0x00001c00
> +#define PCI_LTR_SCALE_SHIFT 10
> +
> +/* Access Control Service */
> +#define PCI_ACS_CAP 0x04 /* ACS Capability Register */
> +#define PCI_ACS_SV 0x01 /* Source Validation */
> +#define PCI_ACS_TB 0x02 /* Translation Blocking */
> +#define PCI_ACS_RR 0x04 /* P2P Request Redirect */
> +#define PCI_ACS_CR 0x08 /* P2P Completion Redirect */
> +#define PCI_ACS_UF 0x10 /* Upstream Forwarding */
> +#define PCI_ACS_EC 0x20 /* P2P Egress Control */
> +#define PCI_ACS_DT 0x40 /* Direct Translated P2P */
> +#define PCI_ACS_CTRL 0x06 /* ACS Control Register */
> +#define PCI_ACS_EGRESS_CTL_V 0x08 /* ACS Egress Control Vector */
> +
> #endif /* LINUX_PCI_REGS_H */
> diff --git a/hw/pcie_aer.c b/hw/pcie_aer.c
> index f08d3c7..be019c7 100644
> --- a/hw/pcie_aer.c
> +++ b/hw/pcie_aer.c
> @@ -38,6 +38,9 @@
> #define PCIE_DEV_PRINTF(dev, fmt, ...) \
> PCIE_DPRINTF("%s:%x "fmt, (dev)->name, (dev)->devfn, ## __VA_ARGS__)
>
> +#define PCI_ERR_SRC_COR_OFFS 0
> +#define PCI_ERR_SRC_UNCOR_OFFS 2
> +
> /* From 6.2.7 Error Listing and Rules. Table 6-2, 6-3 and 6-4 */
> static uint32_t pcie_aer_uncor_default_severity(uint32_t status)
> {
> @@ -320,7 +323,8 @@ static void pcie_aer_msg_root_port(PCIDevice *dev, const PCIEAERMsg *msg)
> if (root_status & PCI_ERR_ROOT_COR_RCV) {
> root_status |= PCI_ERR_ROOT_MULTI_COR_RCV;
> } else {
> - pci_set_word(aer_cap + PCI_ERR_ROOT_COR_SRC, msg->source_id);
> + pci_set_word(aer_cap + PCI_ERR_ROOT_ERR_SRC + PCI_ERR_SRC_COR_OFFS,
> + msg->source_id);
> }
> root_status |= PCI_ERR_ROOT_COR_RCV;
> break;
> @@ -341,7 +345,8 @@ static void pcie_aer_msg_root_port(PCIDevice *dev, const PCIEAERMsg *msg)
> if (root_status & PCI_ERR_ROOT_UNCOR_RCV) {
> root_status |= PCI_ERR_ROOT_MULTI_UNCOR_RCV;
> } else {
> - pci_set_word(aer_cap + PCI_ERR_ROOT_SRC, msg->source_id);
> + pci_set_word(aer_cap + PCI_ERR_ROOT_ERR_SRC +
> + PCI_ERR_SRC_UNCOR_OFFS, msg->source_id);
> }
> root_status |= PCI_ERR_ROOT_UNCOR_RCV;
> }
> --
> 1.7.1
>
--
yamahata
next prev parent reply other threads:[~2011-06-09 10:46 UTC|newest]
Thread overview: 5+ messages / expand[flat|nested] mbox.gz Atom feed top
2011-06-09 7:18 [Qemu-devel] [PATCH] pci: Update pci_regs header Jan Kiszka
2011-06-09 7:39 ` [Qemu-devel] [PATCH] msix: Use replace local defines with pci_regs versions Jan Kiszka
2011-06-09 14:25 ` Michael S. Tsirkin
2011-06-09 10:36 ` Isaku Yamahata [this message]
2011-06-09 14:24 ` [Qemu-devel] [PATCH] pci: Update pci_regs header Michael S. Tsirkin
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