From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([140.186.70.92]:56858) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Qbb8t-0004Z6-Az for qemu-devel@nongnu.org; Tue, 28 Jun 2011 12:28:04 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1Qbb8r-0007oz-PP for qemu-devel@nongnu.org; Tue, 28 Jun 2011 12:28:03 -0400 Received: from dspnet.fr ([188.165.44.67]:54411) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1Qbb8r-0007mr-C2 for qemu-devel@nongnu.org; Tue, 28 Jun 2011 12:28:01 -0400 Date: Tue, 28 Jun 2011 18:27:35 +0200 From: Olivier Galibert Message-ID: <20110628162735.GA21229@dspnet.fr> References: <1309180927-19003-1-git-send-email-avi@redhat.com> <1309180927-19003-2-git-send-email-avi@redhat.com> <20110628100343.GA21866@redhat.com> <4E09ACD2.9070907@siemens.com> <4E09C0B2.3030101@redhat.com> <4E09C3F6.8010702@siemens.com> <4E09C482.6050508@redhat.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <4E09C482.6050508@redhat.com> Subject: Re: [Qemu-devel] [RFC v2 01/20] Hierarchical memory region API List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: qemu-devel@nongnu.org On Tue, Jun 28, 2011 at 03:09:38PM +0300, Avi Kivity wrote: > On 06/28/2011 03:07 PM, Jan Kiszka wrote: > > > > > > The point is that different buses have different widths. > > > target_phys_addr_t matches just one bus in the system. It needs to be > > > the maximum size of all buses present to be useful. > > > > Then we need a type for that. Or we need to demand that > > target_phys_addr_t is defined large enough to support all buses that the > > particular arch wants to address. Hardcoding 64 bit or anything is not > > appropriate for a generic subsystem. > > Okay, let's make t_p_a_t max(bus size in system). Do we have 32-bit > targets that don't support pci (I guess, pc-isa with cpu < ppro?). Do > we want to support a 32-bit variant of pci? It certainly existed at > some point. PCI always had a mechanism for 64-bits addresses even on 32-bits wide bus, called Dual Address Cycle. I'm not sure which was rarer: devices which could handle it, or north bridges which could use it. Probably a tie. But in theory, it was there. OG.